View Z8F0423HH005EC_5100504.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ps024314-0308 copyright ? 2008 by zilog ? , inc. all rights reserved. www.zilog.com product specification high-performance 8-b it microcontrollers z8 encore! xp ? f0823 series
ps024314-0308 do not use in life support life support policy zilog's products are not authorized fo r use as critical components in life support devices or systems without th e express prior written approval of the president and general counsel of zilog corporation. as used herein life support devices or systems are devices which (a) ar e intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordan ce with instructions for use provided in the labeling can be re asonably expected to result in a significant injury to the user. a critical component is any component in a life suppor t device or system whose failure to perform can be reasonably expected to cause the fa ilure of the life support device or system or to affect its safety or effectiveness. document disclaimer ?2008 by zilog, inc. all rights reserved. information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. zilog, inc. does not assume liability for or provide a representation of accuracy of the information, devices, or technology described in this document. zilog also does not assume liability for intellectual property infringement related in any manner to use of information, devices, or technology described herein or otherwise. the information contained within this document has been verified according to the general pr inciples of electrical an d mechanical engineering. z8, z8 encore!, z8 encore! xp, z8 encore! mc, crim zon, ez80, and zneo are trademarks or registered trademarks of zilog, inc. all other product or servi ce names are the property of their respective owners. warning:
ps024314-0308 revision history z8 encore! xp ? f0823 series product specification iii revision history each instance in revision history reflects a change to this docu ment from its previous revision. for more details, re fer to the corresponding pages and appropriate links in the table below. date revision level description page no march 2008 14 changed title to z8 encore! xp f0823 series and the contents to match the title. all december 2007 13 updated title from z8 encore! 8k and 4k series to z8 encore! xp z8f0823 series. updated figure 3 , ta b l e 15 , table 35 , table 59 through table 61 , table 119 , and part number suffix designations section. 8 , 39 , 59 , 91 , 196 , and 226 august 2007 12 updated table 1 , table 16 , and program memory section. 2 , 42 , and 13 june 2007 11 updated to combine z8 encore! 8k and z8 encore! 4k series. all december 2006 10 updated ordering information chapter. 217
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification iv table of contents overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part selection guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 cpu and peripheral overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ez8 cpu features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 10-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . . 5 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 available packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset and stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 voltage brownout reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 external reset indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification v on-chip debugger initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 stop mode recovery using watchdog timer time-out . . . . . . . . . . . . . . . 27 stop mode recovery using a gpio port pin transition . . . . . . . . . . . . . . . 27 stop mode recovery using the external reset pin . . . . . . . . . . . . . . . . . 28 reset register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 peripheral-level power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 power control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 general-purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 gpio port availability by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 gpio alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 direct led drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 shared reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 shared debug pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 crystal oscillator override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5 v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 external clock setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 gpio interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 gpio control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 port a?c address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 port a?c control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 port a?c data direction sub-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 port a?c alternate function sub-registers . . . . . . . . . . . . . . . . . . . . . . . . 45 port a?c input data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 port a?c output data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 led drive enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 led drive level high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 led drive level low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 interrupt vector listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 master interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification vi interrupt vectors and priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 software interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 watchdog timer interrupt assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 interrupt control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt request 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 interrupt request 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 interrupt request 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 irq0 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 60 irq1 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 61 irq2 enable high and low bit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 62 interrupt edge select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 shared interrupt select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 timer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 reading the timer count values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 timer pin signal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 timer 0?1 high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 timer reload high and low byte registers . . . . . . . . . . . . . . . . . . . . . . . . 80 timer 0-1 pwm high and low byte registers . . . . . . . . . . . . . . . . . . . . . . 81 timer 0?1 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 watchdog timer refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 watchdog timer time-out response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 watchdog timer reload unlock sequence . . . . . . . . . . . . . . . . . . . . . . . . 89 watchdog timer control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 89 watchdog timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 watchdog timer reload upper, high and low byte registers . . . . . . . . . . 90 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . 93 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 transmitting data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . 95 transmitting data using the interrupt-driven method . . . . . . . . . . . . . . . . . 96
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification vii receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . . . . 97 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . . . . 98 clear to send (cts) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 multiprocessor (9-bit) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 external driver enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 uart control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart transmit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 uart receive data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart status 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 uart status 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 uart control 0 and control 1 registers . . . . . . . . . . . . . . . . . . . . . . . . . 107 uart address compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 uart baud rate high and low byte registers . . . . . . . . . . . . . . . . . . . . 110 infrared encoder/decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 transmitting irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 receiving irda data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 infrared encoder/decoder control register definitions . . . . . . . . . . . . . . . . . 116 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 automatic powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 single-shot conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 calibration and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 adc control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 adc control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 adc control/status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 adc data high byte register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 adc data low bits register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 comparator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification viii flash information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 flash operation timing using the flash frequency registers . . . . . . . . . 133 flash code protection against external access . . . . . . . . . . . . . . . . . . . . 133 flash code protection against accidental program and erasure . . . . . . . 133 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 flash controller bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 flash controller behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . 136 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . . . 139 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 option bit configuration by reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 option bit types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 reading the flash information page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 flash option bit control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . 143 trim bit address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 trim bit data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash option bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash program memory address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . 144 flash program memory address 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . 145 trim bit address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 trim bit address 0000h?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 trim bit address 0001h?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 trim bit address 0002h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 trim bit address 0003h?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 trim bit address 0004h?reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 zilog calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 adc calibration data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 serialization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 randomized lot identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 on-chip debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification ix operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 ocd interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 ocd data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ocd auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 ocd serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 ocd unlock sequence (8-pin devices only) . . . . . . . . . . . . . . . . . . . . . . 156 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 runtime counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 on-chip debugger commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 on-chip debugger control register definitions . . . . . . . . . . . . . . . . . . . . . . . 161 ocd control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 ocd status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 oscillator control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 system clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 clock failure detection and recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 oscillator control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 internal precision oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 ez8 cpu instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 assembly language programming introduction . . . . . . . . . . . . . . . . . . . . . . . 171 assembly language syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ez8 cpu instruction notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 ez8 cpu instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 ez8 cpu instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 opcode maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 on-chip peripheral ac and dc electrical characteristics . . . . . . . . . . . . . . . 199 general purpose i/o port input data sample timing . . . . . . . . . . . . . . . . 202 general purpose i/o port output timing . . . . . . . . . . . . . . . . . . . . . . . . . 204 on-chip debugger timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 uart timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
ps024314-0308 table of contents z8 encore! xp ? f0823 series product specification x ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 part number suffix designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 1 overview zilog?s z8 encore! xp ? microcontroller unit (mcu) family of products are the first zilog ? microcontroller products based on the 8-bit ez8 cpu core. z8 encore! xp f0823 series products expand upon zilog?s extensive line of 8-bit microcontrollers. the flash in-circuit programming capability allows for faster developm ent time and program changes in the field. the new ez8 cpu is upward compatib le with existing z8 ? instruc- tions. the rich peripheral set of z8 encore! xp f0823 series makes it suitable for a vari- ety of applications including motor control, security systems, home appliances, personal electronic devices, and sensors. features the key features of z8 encore! xp f0823 series include: ? 5 mhz ez8 cpu ? 1 kb, 2 kb, 4 kb, or 8 kb flash memory with in-circuit programming capability ? 256 b, 512 b, or 1 kb register ram ? 6 to 24 i/o pins depending upon package ? internal precision oscillator (ipo) ? full-duplex uart ? the universal asynchronous receiver/transmitter (uart) baud rate generator (brg) can be configured and used as a basic 16-bit timer ? infrared data associat ion (irda)-compliant infrared en coder/decoders, integrated with uart ? two enhanced 16-bit timers with ca pture, compare, and pwm capability ? watchdog timer (wdt) with dedi cated internal rc oscillator ? on-chip debugger (ocd) ? optional 8-channel, 10-bit anal og-to-digital converter (adc) ? on-chip analog comparator ? up to 20 vectored interrupts ? direct led drive with programmable drive strengths ? voltage brownout (vbo) protection ? power-on reset (por)
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 2 ? 2.7 v to 3.6 v operating voltage ? up to thirteen 5 v-tolerant input pins ? 8-, 20-, and 28-pin packages ? 0 c to +70 c and -40 c to +105 c for operating temperature ranges part selection guide table 1 lists the basic features and package styl es available for each device within the z8 encore! xp ? f0823 series product line. table 1. z8 encore! xp f0823 series family part selection guide part number flash (kb) ram (b) i/o adc inputs packages z8f0823 8 1024 6?22 4?8 8-, 20-, and 28-pins z8f0813 8 1024 6?24 0 8-, 20-, and 28-pins z8f0423 4 1024 6?22 4?8 8-, 20-, and 28-pins z8f0413 4 1024 6?24 0 8-, 20-, and 28-pins z8f0223 2 512 6?22 4?8 8-, 20-, and 28-pins z8f0213 2 512 6?24 0 8-, 20-, and 28-pins z8f0123 1 256 6?22 4?8 8-, 20-, and 28-pins z8f0113 1 256 6?24 0 8-, 20-, and 28-pins
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 3 block diagram figure 1 on page 3 displays the block diagram of the architecture of z8 encore! xp f0823 series devices. figure 1. z8 encore! xp ? f0823 series block diagram gpio irda uart timers adc flash flash controller ram ram controller memory interrupt controller on-chip debugger ez8 cpu wdt por/vbo and reset controller register bus memory busses system clock comparator low power rc oscillator oscillator control internal precision oscillator
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 4 cpu and peripheral overview ez8 cpu features the ez8 cpu, zilog?s latest 8-bit central processing unit (cpu), meets the continuing demand for faster and code-efficient microcon trollers. the ez8 cpu executes a superset of the original z8 ? instruction set. the ez8 cpu features include: ? direct register-to-register architecture allows each register to function as an accumulator, improving execution time and decreasing the required program memory. ? software stack allows much greater dept h in subroutine calls and interrupts than hardware stacks. ? compatible with existing z8 code. ? expanded internal register file allows access of up to 4 kb. ? new instructions improve execution efficiency for code developed using higher-level programming languages, including c. ? pipelined instruction fetch and execution. ? new instructions for improv ed performance including bit, bswap, btj, cpc, ldc, ldci, lea, mult, and srl. ? new instructions support 12-bit linear addressing of the register file. ? up to 10 mips operation. ? c-compiler friendly. ? 2 to 9 clock cycles per instruction. for more information on ez8 cpu, refer to ez8 cpu core user manual (um0128) avail- able for download at www.zilog.com . general-purpose i/o z8 encore! xp f0823 series features 6 to 24 port pins (ports a?c) for general-purpose i/o (gpio). the number of gpio pins available is a function of package. each pin is individually programmable. 5 v tolerant input pins are available on all i/os on 8-pin devices, most i/os on other package types. flash controller the flash controller programs and erases fl ash memory. the flash controller supports protection against accidental pr ogram and erasure, as well as factory serialization and read protection.
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 5 internal precision oscillator the internal precision oscillator (ipo) is a trimmable clock source that requires no external components. 10-bit analog-to-dig ital converter the optional analog-to-digital co nverter (adc) converts an analog input signal to a 10-bit binary number. the adc accepts inputs from eigh t different analog input pins in both sin- gle-ended and differential modes. analog comparator the analog comparator compares the signal at an input pin with either an internal programmable voltage reference or a second in put pin. the comparator output can be used to drive either an output pin or to generate an interrupt. universal asynchronous receiver/transmitter the uart is full-duplex and capable of handling asynchronous data transfers. the uart supports 8- and 9-bit data modes and select able parity. the uart also supports multi- drop address processing in hardware. the uart baud rate generator can be configured and used as a basic 16-bit timer. timers two enhanced 16-bit reloadable timers can be used for timing/counting events or for motor control operations. these timers provid e a 16-bit programmable reload counter and operate in one-shot, continuous, gated, capture, capture restart, compare, capture and compare, pwm single output, and pwm dual output modes. interrupt controller z8 encore! xp ? f0823 series products support up to 20 interrupts. these interrupts consist of eight internal peri pheral interrupts and 12 general-purpose i/o pin interrupt sources. the interrupts have three levels of programmable interrupt priority.
ps024314-0308 overview z8 encore! xp ? f0823 series product specification 6 reset controller z8 encore! xp ? f0823 series products ca n be reset using the reset pin, por, wdt time-out, stop mode exit, or voltag e brownout warning signal. the reset pin is bidirectional, that is, it functions as reset source as well as a reset indicator. on-chip debugger z8 encore! xp f0823 series products feature an integrated on-chip debugger. the ocd provides a rich-set of debuggi ng capabilities, such as reading and writing registers, pro- gramming flash memory, se tting breakpoints and execu ting code. a single-pin interface provides comm unication to the ocd.
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 7 pin description z8 encore! xp ? f0823 series products are available in a variety of package styles and pin configurations. this chapter describes the signals and pin configurations available for each of the package styles. fo r information on physical package specifications, see pack- aging on page 209. available packages table 2 lists the package styles that are availabl e for each device in the z8 encore! xp f0823 series product line. pin configurations figure 2 through figure 4 displays the pin configurations for all packages available in the z8 encore! xp f0823 series. for description of signals, see table 3 . the analog input alternate functions (ana x ) are not available on the z8f0x1 3 devices. the analog supply pins (av dd and av ss ) are also not available on these pa rts, and are replaced by pb6 and pb7. at reset, all pins of ports a, b, and c defau lt to an input state. in addition, any alternate functionality is not enabled, so the pins function as general-purpose input ports until programmed otherwise. table 2. z8 encore! xp f0823 series package options part number adc 8-pin pdip 8-pin soic 20-pin pdip 20-pin soic 20-pin ssop 28-pin pdip 28-pin soic 28-pin ssop 8-pin qfn/ mlf-s z8f0823 yes x x x x x x x x x z8f0813 no x x x x x x x x x z8f0423 yes x x x x x x x x x z8f0413 no x x x x x x x x x z8f0223 yes x x x x x x x x x z8f0213 no x x x x x x x x x z8f0123 yes x x x x x x x x x z8f0113 no x x x x x x x x x
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 8 the pin configurations listed are preliminary and subject to change based on manufactur- ing limitations. figure 2. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 8-pin soic, qfn/mlf-s, or pdip package* figure 3. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 20-pin soic, ssop or pdip package* figure 4. z8f08x3, z8f04x3, f02x3 and z8f01x3 in 28-pin soic, ssop or pdip package* vss pa5/txd0/t1out /ana0/cinp pa4/rxd0/ana1/cinn pa3/cts0 /ana2/cout/t1in vdd pa0/t0in/t0out /dbg pa1/t0out/ana3/vref/clkin pa2/reset /de0/t1out 2 1 3 4 7 8 6 5 pb0/ana0 pc3/cout/led pc2/ana6/led/vref pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset pa7/t1out pa6/t1in/t1out pb1/ana1 pb2/ana2 pb3/clkin/ana3 vdd pa0/t0in/t0out pa1/t0out vss pa2/de0 1 pa5/txd0 pa3/cts0 5 10 pa4/rxd0 2 3 4 6 7 8 9 20 16 11 19 18 17 15 14 13 12 pb1/ana1 pb0/ana0 pc3/cout/led pc2/ana6/led pc1/ana5/cinn/led pc0/ana4/cinp/led dbg reset pc7/led pb2/ana2 pb3/clkin/ana3 pb4/ana7 pb5/vref (pb6) avdd vdd pa0/t0in/t0out pa1/t0out 1 pc6/led vss 5 10 (pb7) avss pa2/de0 pa3/cts0 pa4/rxd0 14 pa5/txd0 2 3 4 6 7 8 9 11 12 13 pc5/led pc4/led pa7/t1out pa6/t1in/t1out 28 24 19 15 27 26 25 23 22 21 20 18 17 16
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 9 * analog input alternate functions (ana) ar e not available on the z8f0x13 devices. signal descriptions table 3 lists the z8 encore! xp ? f0823 series signals. to determine the signals available for the specific package styles, see pin configurations on page 7. table 3. signal descriptions signal mnemonic i/o description general-purpose i/o ports a?d pa[7:0] i/o port a. these pins are used for general-purpose i/o. pb[7:0] i/o port b. these pins are used for general-purpose i/o. pb6 and pb7 are available only in those devices without an adc. pc[7:0] i/o port c. these pins are used for general-purpose i/o. note: pb6 and pb7 are only available in 28-pin packages wi thout adc. in 28-pin packages with adc, they are replaced by av dd and av ss . uart controllers txd0 o transmit data. this signal is the tr ansmit output from the uart and irda. rxd0 i receive data. this signal is the receive input for the uart and irda. cts0 i clear to send. this signal is the flow control input for the uart. de o driver enable. this signal allows au tomatic control of external rs-485 drivers. this signal is approximat ely the inverse of the txe (transmit empty) bit in the uart status 0 register. the de signal can be used to ensure the external rs-485 driver is enabled when data is transmitted by the uart. timers t0out/t1out o timer output 0?1. these signals are output from the timers. t0out /t1out o timer complement output 0?1. these signals are output from the timers in pwm dual output mode. t0in/t1in i timer input 0?1. these signals are used as the capture, gating and counter inputs. the t0in signal is multiplexed t0out signals. comparator cinp/cinn i comparator inputs. these signals are the positive and negative inputs to the comparator. cout o comparator output. this is the output of the comparator. note:
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 10 pin characteristics table 4 provides detailed information about the ch aracteristics for each pin available on z8 encore! xp f0823 series 20 - and 28-pin devices. data in table 4 is sorted alphabeti- cally by the pin symbol mnemonic. analog ana[7:0] i analog port. these signals are used as inputs to the adc. the ana0, ana1, and ana2 pins can also acce ss the inputs and output of the integrated transimpedance amplifier. vref i/o analog-to-digital converter reference voltage input. clock input clkin i clock input signal. this pin can be used to input a ttl-level signal to be used as the system clock. led drivers led o direct led drive capability. all port c pins have the cap ability to drive an led without any other external components. these pins have programmable drive strengths set by the gpio block. on-chip debugger dbg i/o debug. this signal is the control and data input and output to and from the ocd. the dbg pin is open-drain and requires an external pull- up resistor to ensure proper operation. reset reset i/o reset. generates a reset when asserted (driven lo w). also serves as a reset indicator; the z8 en core! xp forces this pin low when in reset. this pin is open-drain and features an enabled internal pull-up resistor. power supply v dd i digital power supply. av dd i analog power supply. v ss i digital ground. av ss i analog ground. note: the av dd and av ss signals are available only in 28-pin packages with adc. they are replaced by pb6 and pb7 on 28-pin packages without adc. table 3. signal descriptions (continued) signal mnemonic i/o description caution:
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 11 table 5 provides detailed information about the ch aracteristics for each pin available on z8 encore! xp ? f0823 series 8-pin devices. all six i/o pins on the 8-pin packages are 5 v-tolerant (unless the pull-up devices are enabled). the column in table 4 below describes 5 v-tolerance for the 20- and 28-pin packages only. pb6 and pb7 are available only in the devices without adc. table 4. pin characteristics (20- and 28-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull-up or pull-down schmitt- trigger input open drain output 5 v tolerance avdd n/a n/a n/a n/a n/a n/a n/a n/a avss n/a n/a n/a n/a n/a n/a n/a na dbg i/o i n/a yes no yes yes yes pa[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pa[7:2] only pb[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pb[7:6] only pc[7:0] i/o i n/a yes programmable pull-up yes yes, programmable pc[7:3] only reset i/o i/o (defaults to reset ) low (in reset mode) yes (pd0 only) always on for reset yes always on for reset yes vdd n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a note: note:
ps024314-0308 pin description z8 encore! xp ? f0823 series product specification 12 ) table 5. pin characteristics (8-pin devices) symbol mnemonic direction reset direction active low or active high tristate output internal pull-up or pull-down schmitt- trigger input open drain output 5 v tolerance pa0/dbg i/o i (but can change during reset if key sequence detected) n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled pa1 i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled reset / pa2 i/o i/o (defaults to reset ) n/a yes programmable for pa2; always on for reset yes programmable for pa2; always on for reset yes, unless pull-ups enabled pa[5:3] i/o i n/a yes programmable pull-up yes yes, programmable yes, unless pull-ups enabled vdd n/a n/a n/a n/a n/a n/a n/a n/a vss n/a n/a n/a n/a n/a n/a n/a n/a
ps024314-0308 address space z8 encore! xp ? f0823 series product specification 13 address space the ez8 cpu can access three distinct address spaces: ? the register file contains addresses for th e general-purpose registers and the ez8 cpu, peripheral, and general-purpos e i/o port control registers. ? the program memory contains addresses fo r all memory locations having executable code and/or data. ? the data memory contains addresses for all memory locations that contain data only. these three address spaces are covered brie fly in the following subsections. for more detailed information regarding the ez8 cpu and its address space, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . register file the register file address space in the z8 encore! xp ? mcu is 4 kb (4096 bytes). the register file is composed of two sections: co ntrol registers and general-purpose registers. when instructions are executed, registers defined as sources are read, and registers defined as destinations are written. the architecture of the ez8 cpu allows all general-purpose registers to function as accumulators, address pointers, index registers, stack areas, or scratch pad memory. the upper 256 bytes of the 4 kb register file address space are reserved for control of the ez8 cpu, the on-chip peripherals, and the i/o ports. these registers are located at addresses from f00h to fffh . some of the addresses within the 256 b control register section are reserved (unavailable). reading fro m a reserved register file address returns an undefined value. writing to reserved register file addr esses is not recommended and can produce unpredictable results. the on-chip ram always begins at address 000h in the register file address space. z8 encore! xp f0823 series devices contain 256 b-1 kb of on-chip ram. reading from register file addresses outside the availabl e ram addresses (and not within the control register address space) returns an undefined va lue. writing to these register file addresses produces no effect. program memory the ez8 cpu supports 64 kb of program me mory address space. z8 encore! xp f0823 series devices contain 1 kb to 8 kb of on-chip flash memory in the program memory address space. reading from program memory addresses outside the available flash
ps024314-0308 address space z8 encore! xp ? f0823 series product specification 14 memory addresses returns ffh . writing to these unimplemented program memory addresses produces no effect. table 6 describes the program me mory maps for the z8 encore! xp ? f0823 series products. table 6. z8 encore! xp f0823 series program memory maps program memory address (hex) function z8f0823 and z8f0813 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?0fff program memory z8f0423 and z8f0413 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?0fff program memory z8f0223 and z8f0213 products 0000?0001 flash option bits 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?07ff program memory z8f0123 and z8f0113 products 0000?0001 flash option bits
ps024314-0308 address space z8 encore! xp ? f0823 series product specification 15 data memory z8 encore! xp ? f0823 series does not use the ez8 cpu?s 64 kb data memory address space. flash information area table 7 lists the z8 encore! xp f0823 seri es flash information area. this 128 b information area is accessed by setting bit 7 of the flash page select register to 1. when access is enabled, the flash information area is mapped into the program memory and overlays the 128 bytes at addresses fe00h to ff7fh . when the information area access is enabled, all reads from these program memory addresses return the information area data rather than the program memory data. access to the flash informatio n area is read-only. 0002?0003 reset vector 0004?0005 wdt interrupt vector 0006?0007 illegal instruction trap 0008?0037 interrupt vectors* 0038?003d oscillator fail traps* 003e?03ff program memory *see table 33 on page 54 for a list of the interrupt vectors and traps. table 7. z8 encore! xp f0823 series flash memory information area map program memory address (hex) function fe00?fe3f zilog option bits. fe40?fe53 part number. 20-character ascii alphanumeric code left justified and filled with fh . fe54?fe5f reserved. fe60?fe7f zilog calibration data. fe80?ffff reserved. table 6. z8 encore! xp f0823 series program memory maps (continued) program memory address (hex) function
ps024314-0308 address space z8 encore! xp ? f0823 series product specification 16
ps024314-0308 register map z8 encore! xp ? f0823 series product specification 17 register map table 8 lists the address map for the regi ster file of the z8 encore! xp ? f0823 series devices. not all devices and package styles in the z8 encore! xp f0823 series support the adc, or all gpio ports. consider register s for unimplemented peripherals as reserved. table 8. register file address map address (hex) register description mnemonic reset (hex) page no general-purpose ram z8f0823/z8f0813 devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f0423/z8f0413 devices 000?3ff general-purpose register file ram ? xx 400?eff reserved ? xx z8f0223/z8f0213 devices 000?1ff general-purpose register file ram ? xx 200?eff reserved ? xx z8f0123/z8f0113 devices 000?0ff general-purpose register file ram ? xx 100?eff reserved ? xx timer 0 f00 timer 0 high byte t0h 00 80 f01 timer 0 low byte t0l 01 80 f02 timer 0 reload high byte t0rh ff 81 f03 timer 0 reload low byte t0rl ff 81 f04 timer 0 pwm high byte t0pwmh 00 81 f05 timer 0 pwm low byte t0pwml 00 82 f06 timer 0 control 0 t0ctl0 00 82 f07 timer 0 control 1 t0ctl1 00 83 timer 1 f08 timer 1 high byte t1h 00 80 f09 timer 1 low byte t1l 01 80 f0a timer 1 reload high byte t1rh ff 81 f0b timer 1 reload low byte t1rl ff 81
ps024314-0308 register map z8 encore! xp ? f0823 series product specification 18 f0c timer 1 pwm high byte t1pwmh 00 81 f0d timer 1 pwm low byte t1pwml 00 82 f0e timer 1 control 0 t1ctl0 00 82 f0f timer 1 control 1 t1ctl1 00 80 f10?f3f reserved ? xx uart f40 uart0 transmit data u0txd xx 104 uart0 receive data u0rxd xx 105 f41 uart0 status 0 u0stat0 0000011xb 105 f42 uart0 control 0 u0ctl0 00 107 f43 uart0 control 1 u0ctl1 00 107 f44 uart0 status 1 u0stat1 00 106 f45 uart0 address compare u0addr 00 109 f46 uart0 baud rate high byte u0brh ff 110 f47 uart0 baud rate low byte u0brl ff 110 f48?f6f reserved ? xx analog-to-digital converter (adc) f70 adc control 0 adcctl0 00 122 f71 adc control 1 adcctl1 80 122 f72 adc data high byte adcd_h xx 124 f73 adc data low bits adcd_l xx 124 f74?f7f reserved ? xx low power control f80 power control 0 pwrctl0 80 33 f81 reserved ? xx led controller f82 led drive enable leden 00 51 f83 led drive level high byte ledlvlh 00 51 f84 led drive level low byte ledlvll 00 52 f85 reserved ? xx oscillator control f86 oscillator control oscctl a0 167 f87?f8f reserved ? xx comparator 0 f90 comparator 0 control cmp0 14 128 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps024314-0308 register map z8 encore! xp ? f0823 series product specification 19 f91?fbf reserved ? xx interrupt controller fc0 interrupt request 0 irq0 00 58 fc1 irq0 enable high bit irq0enh 00 60 fc2 irq0 enable low bit irq0enl 00 61 fc3 interrupt request 1 irq1 00 59 fc4 irq1 enable high bit irq1enh 00 62 fc5 irq1 enable low bit irq1enl 00 62 fc6 interrupt request 2 irq2 00 60 fc7 irq2 enable high bit irq2enh 00 63 fc8 irq2 enable low bit irq2enl 00 63 fc9?fcc reserved ? xx fcd interrupt edge select irqes 00 64 fce shared interrupt select irqss 00 64 fcf interrupt control irqctl 00 65 gpio port a fd0 port a address paaddr 00 43 fd1 port a control pactl 00 45 fd2 port a input data pain xx 45 fd3 port a output data paout 00 45 gpio port b fd4 port b address pbaddr 00 43 fd5 port b control pbctl 00 45 fd6 port b input data pbin xx 45 fd7 port b output data pbout 00 45 gpio port c fd8 port c address pcaddr 00 43 fd9 port c control pcctl 00 45 fda port c input data pcin xx 45 fdb port c output data pcout 00 45 fdc?fef reserved ? xx watchdog timer (wdt) ff0 reset status rststat xx 90 watchdog timer control wdtctl xx 90 ff1 watchdog timer reload upper byte wdtu ff 91 table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps024314-0308 register map z8 encore! xp ? f0823 series product specification 20 ff2 watchdog timer reload high byte wdth ff 91 ff3 watchdog timer reload low byte wdtl ff 91 ff4?ff5 reserved ? xx trim bit control ff6 trim bit address trmadr 00 143 ff7 trim data trmdr xx 144 flash memory controller ff8 flash control fctl 00 137 ff8 flash status fstat 00 137 ff9 flash page select fps 00 138 flash sector protect fprot 00 139 ffa flash programming frequency high byte ffreqh 00 140 ffb flash programming frequency low byte ffreql 00 140 ez8 cpu ffc flags ? xx refer to ez8 cpu core user manual (um0128) ffd register pointer rp xx ffe stack pointer high byte sph xx fff stack pointer low byte spl xx xx=undefined table 8. register file address map (continued) address (hex) register description mnemonic reset (hex) page no
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 21 reset and stop mode recovery the reset controller within the z8 encore! xp ? f0823 series controls reset and stop mode recovery operation and provides indication of low su pply voltage conditions. in typical operation, the following events cause a reset: ? power-on reset (por) ? voltage brownout (vbo) ? watchdog timer time-out (when configured by the wdt_res flash option bit to initiate a reset) ? external reset pin assertion (when the alternate reset function is enabled by the gpio register) ? on-chip debugger initiated reset (ocdctl[0] set to 1) when the device is in stop mode, a stop mode recovery is initiated by either of the following: ? watchdog timer time-out ? gpio port input pin transition on an enabled stop mode recovery source the vbo circuitry on the device performs the follo wing function: ? generates the vbo reset when the supply voltage drops below a minimum safe level reset types z8 encore! xp f0823 series provides several different types of reset operation. stop mode recovery is considered a form of reset. table 9 lists the types of reset and their operating characteristics. the sy stem reset is longer if the external crystal oscillator is enabled by the flash option bits, allowing additional time for oscillator start-up.
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 22 during a system reset or stop mode recovery, the ipo requires 4 s to start up. then the z8 encore! xp f0823 series device is held in reset for 66 cycles of the internal precision oscillator. if the crystal oscillator is enabled in the flash option bits, this reset period is increased to 5000 ipo cycles. when a reset oc curs because of a low voltage condition or power-on reset, this delay is measured from the time that the supply voltage first exceeds the por level. if the external pin reset remain s asserted at the end of the reset period, the device remains in reset until the pin is deasserted. at the beginning of reset, all gpio pins ar e configured as inputs with pull-up resistor disabled. during reset, the ez8 cpu and on-chip peripher als are idle; however, the on-chip crystal oscillator and watchdog timer oscillator continue to run. upon reset, control registers w ithin the register file that have a defined reset value are loaded with their reset values. other control registers (including the stack pointer, regis- ter pointer, and flags) and general-purpo se ram are undefined following reset. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program counter. prog ram execution begins at the reset vector address. when the control registers are re-initialized by a system reset, the system clock after reset is always the ipo. the software must reconfig ure the oscillator control block, such that the correct system clock source is enabled and selected. reset sources table 10 lists the possible sources of a system reset. table 9. reset and stop mode recovery characteristics and latency reset type reset characteristics and latency control registers ez8 cpu reset latency (delay) system reset reset (as applicable) reset 66 intern al precision oscillator cycles stop mode recovery unaffected, except wdt_ctl and osc_ctl registers reset 66 internal precision oscillator cycles + ipo startup time
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 23 power-on reset each device in the z8 encore! xp f0823 seri es contains an internal por circuit. the por circuit monitors the supply voltage and holds the device in the reset state until the supply voltage reaches a safe operating level. after the supply voltage exceeds the por voltage threshold (v por ), the device is held in the r eset state until the por counter has timed out. if the crystal oscillator is enable d by the option bits, this time-out is longer. after the z8 encore! xp f0823 series device ex its the por state, the ez8 cpu fetches the reset vector. following the por, the por status bit in watchdog timer control (wdtctl) register is set to 1. figure 5 displays por operation. fo r the por threshold voltage (v por ), see electrical characteristics on page 193. table 10. reset sources and resulting reset type operating mode reset source special conditions normal or halt modes power-on reset/voltage brownout reset delay begins after supply voltage exceeds por level. watchdog timer time-out when configured for reset none. reset pin assertion all reset pulses less than three system clocks in width are ignored. ocd initiated reset (ocdctl[0] set to 1) system reset, except the ocd is unaffected by the reset. stop mode power-on reset/voltage brownout reset delay begins after supply voltage exceeds por level. reset pin assertion all reset pulses less than the specified analog delay are ignored. see electrical characteristics on page 193. dbg pin driven low none.
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 24 figure 5. power-on reset operation voltage brownout reset the devices in the z8 encore! xp f0823 se ries provide low vbo protection. the vbo circuit senses when the supply voltage drops to an unsafe level (below the vbo threshold voltage) and forces the device into the reset state. while the supply voltage remains below the por voltage threshold (v por ), the vbo block holds the device in the reset. after the supply voltage again exceeds the po wer-on reset voltage threshold, the device progresses through a full system reset se quence, as described in the por section. following por, the por status bit in the rese t status (rststat) register is set to 1. figure 6 displays voltage brownout operation. for the vbo and por threshold voltages (v vbo and v por ), see electrical characteristics on page 193. the vbo circuit can be either enabled or di sabled during stop mode. operation during stop mode is set by the vbo_ao flash op tion bit. for information on configuring vbo_ao, see flash option bits on page 141. v cc = 0.0 v v cc = 3.3 v v por v vbo internal precision internal reset signal program execution por counter delay oscillator note: not to scale
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 25 figure 6. voltage brownout reset operation the por level is greater than the vbo leve l by the specified hysteresis value. this ensures that the device undergoes a po r after recovering from a vbo condition. watchdog timer reset if the device is in normal or stop mode, the watchdog timer can initiate a system reset at time-out if the wdt_res flash optio n bit is programmed to 1. this is the unprogrammed state of the wdt_res flash option bit. if the bit is programmed to 0, it configures the watchdog timer to cause an interrupt, not a system reset, at time-out. the wdt status bit in the wdt control regist er is set to signify that the reset was initiated by the watchdog timer. external reset input the reset pin has a schmitt-triggered input and an internal pull-up resistor. once the reset pin is asserted for a minimum of four sy stem clock cycles, th e device progresses through the system reset sequen ce. because of the possible asynchronicity of the system v cc = 3.3 v v por v vbo internal reset signal program execution program execution voltage brownout v cc = 3.3 v system clock wdt clock por counter delay note: not to scale
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 26 clock and reset signals, the required reset duration can be as short as three clock periods and as long as four. a reset pulse three cloc k cycles in duration might trigger a reset; a pulse four cycles in duration always triggers a reset. while the reset input pin is asserted low, the z8 encore! xp f0823 series devices remain in the reset state. if the reset pin is held low beyond the system reset time- out, the device exits the reset state on th e system clock rising edge following reset pin deassertion. following a system re set initiated by the external reset pin, the ext sta- tus bit in the wdt control (wdtctl) register is set to 1. external reset indicator during system reset or when en abled by the gpio logic (see port a?c control registers on page 44), the reset pin functions as an open-drain (a ctive low) reset mode indicator in addition to the input functionality. this re set output feature allows an z8 encore! xp f0823 series device to reset other components to which it is connected, even if that reset is caused by internal sources such as por, vbo, or wdt events. after an internal reset even t occurs, the internal circu itry begins driving the reset pin low. the reset pin is held low by the internal circuitry until the appropriate delay listed in table 9 has elapsed. on-chip debugger initiated reset a por is initiated using the on -chip debugger by setting the rst bit in the ocd control register. the ocd block is not reset but the re st of the chip goes through a normal system reset. the rst bit automatically clears duri ng the system reset. following the system reset, the por bit in the reset status (rststat) register is set. stop mode recovery the device enters into stop mode when ez8 cpu executes a stop instruction. for more details on stop mode, see low-power modes on page 31. during stop mode recovery, the cpu is held in reset for 66 ipo cycles if the crystal oscillator is disabled or 5000 cycles if it is enabled. the smr delay also incl uded the time required to start up the ipo. stop mode recovery does not affect on-chi p registers other than the watchdog timer control register (wdtctl) and the oscilla tor control register (oscctl). after any stop mode recovery, the ipo is enabled an d selected as the system clock. if another system clock source is required or ipo di sabling is required, the stop mode recovery code must reconfigure the oscillator contro l block such that the correct system clock source is enabled and selected. the ez8 cpu fetches the reset vector at program memory addresses 0002h and 0003h and loads that value into the program coun ter. program execution begins at the reset
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 27 vector address. following stop mode recove ry, the stop bit in the watchdog timer control register is set to 1. table 11 lists the stop mode reco very sources and resulting actions. the section following th e table provides more detaile d information on each of the stop mode recovery sources. stop mode recovery usin g watchdog timer time-out if the watchdog timer times out during stop mode, the device undergoes a stop mode recovery sequence. in the wa tchdog timer control register, the wdt and stop bits are set to 1. if the watchdog timer is configured to generate an interrupt upon time-out and z8 encore! xp ? f0823 series device is configured to respond to interrupts, the ez8 cpu services the watchdog timer interrupt request following the normal stop mode recovery sequence. stop mode recovery using a gpio port pin transition each of the gpio port pins can be configured as a stop mode recovery input source. on any gpio pin enabled as a stop mode recove ry source, a change in the input pin value (from high to low or from low to hi gh) initiates stop mode recovery. the smr pulses shorter than specified does no t trigger a recovery. when this happens, the stop bit in the reset status (rststat) register is set to 1. in stop mode, the gpio port input data re gisters (pxin) are disabled. the port input data registers record the port transition only if the signal stays on the port pin through the end of the stop mode recovery delay. as a result, short pulses on the port pin can initiate stop mode recovery without being wr itten to the port input data register or without initiating an interrup t (if enabled for that pin). table 11. stop mode recovery sources and resulting action operating mode stop mode recovery source action stop mode watchdog timer time-out when configured for reset stop mode recovery watchdog timer time-out when configured for interrupt stop mode recovery followed by interrupt (if interrupts are enabled) data transition on any gpio port pin enabled as a stop mode recovery source stop mode recovery assertion of external reset pin system reset debug pin driven low system reset note: caution:
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 28 stop mode recovery us ing the external reset pin when the z8 encore! xp f082 3 series device is in stop mode and the external reset pin is driven low, a system reset occurs. because of a glitch filter operating on the reset pin, the low pulse must be gr eater than the minimum width sp ecified, or it is ignored. for more details, see electrical characteristics on page 193. reset register definitions reset status register the reset status (rststat) register is a read-o nly register that indicates the source of the most recent reset event, indicates a st op mode recovery ev ent, and indicates a watchdog timer time-out. reading this regi ster resets the upper four bits to 0. this register shares its address with the watc hdog timer control register, which is write- only ( table 12 ). por?power-on reset indicator if this bit is set to 1, a powe r-on reset event is occurred. this bit is reset to 0 if a wdt time-out or stop mode recovery occurs. this bi t is also reset to 0 when the register is read. table 12. reset status register (rststat) bits 7 6 5 4 3 2 1 0 field por stop wdt ext reserved reset see descriptions below 0 0 0 0 0 r/w rrrrrrrr addr ff0h reset or stop mode recovery event por stop wdt ext power-on reset 1 0 0 0 reset using reset pin assertion 0 0 0 1 reset using wdt time-out 0 0 1 0 reset using the ocd (octctl[1] set to 1) 1 0 0 0 reset from stop mode using dbg pin driven low 1 0 0 0 stop mode recovery using gpio pin transition 0 1 0 0 stop mode recovery using wdt time-out 0 1 1 0
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 29 stop?stop mode recovery indicator if this bit is set to 1, a stop mode recovery is occurred. if the stop and wdt bits are both set to 1, the stop mode recovery o ccurred because of a wdt time-out. if the stop bit is 1 and the wdt bit is 0, the stop mode recovery w as not caused by a wdt time-out. this bit is reset by a por or a wd t time-out that occurred while not in stop mode. reading this register also resets this bit. wdt?watchdog timer time-out indicator if this bit is set to 1, a wdt time-out occu rred. a por resets this pin. a stop mode recovery from a change in an input pin also reset s this bit. reading this register resets this bit. this read must occur befo re clearing the wdt interrupt. ext?external reset indicator if this bit is set to 1, a reset initiated by the external reset pin occurred. a power-on reset or a stop mode recovery from a change in an input pin resets this bit. reading this register resets this bit. reserved?0 when read
ps024314-0308 reset and stop mode recovery z8 encore! xp ? f0823 series product specification 30
ps024314-0308 low-power modes z8 encore! xp ? f0823 series product specification 31 low-power modes z8 encore! xp ? f0823 series products contain power-saving features. the highest level of power reduction is provided by the stop mode, in which nearly all device functions are powered down. the next lower level of power reduction is provided by the halt mode, in which the cpu is powered down. further power savings can be implemented by disabling individual peripheral blocks while in active mode (defined as being in neither stop nor halt mode). stop mode executing the ez8 cpu?s stop instruction pl aces the device into stop mode, powering down all peripherals except the voltage brow nout detector, and the watchdog timer. these two blocks may also be disabled for additional power savings. in stop mode, the operating characteristics are: ? primary crystal oscillator and in ternal precision oscillator are stopped; xin and xout (if previously enabled) are disabled, and pa0/pa 1 revert to the states programmed by the gpio registers. ? system clock is stopped. ? ez8 cpu is stopped. ? program counter (pc) stops incrementing. ? watchdog timer?s internal rc os cillator continues to operate if enabled by the oscillator control register. ? if enabled, the watchdog timer logic continues to operate. ? if enabled for operation in stop mode by th e associated flash option bit, the voltage brownout protection circuit continues to operate. ? all other on-chip peripherals are idle. to minimize current in stop mode, all gpio pins that are configured as digital inputs must be driven to one of the supply rails (v cc or gnd). additionally, any gpios config- ured as outputs must also be driven to one of the supply rails. the device can be brought out of stop mode using stop mode recovery. for more information on stop mode recovery, see reset and stop mode recovery on page 21.
ps024314-0308 low-power modes z8 encore! xp ? f0823 series product specification 32 halt mode executing the ez8 cpu?s halt instruction places the devi ce into halt mode, which powers down the cpu but leaves all other peripherals active. in halt mode, the operating characteristics are: ? primary oscillator is enable d and continues to operate. ? system clock is enabled and continues to operate. ? ez8 cpu is stopped. ? program counter stops incrementing. ? watchdog timer?s internal rc os cillator continues to operate. ? if enabled, the watchdog timer continues to operate. ? all other on-chip periphera ls continue to operate. the ez8 cpu can be brought out of halt mode by any of the following operations: ? interrupt ? watchdog timer time-out (interrupt or reset) ? power-on reset ? voltage brownout reset ? external reset pin assertion to minimize current in halt mode, all gpio pins that are configured as inputs must be driven to one of the supply rails (v cc or gnd). peripheral-level power control in addition to the stop and halt modes, it is possible to disable each peripheral on each of the z8 encore! xp f0823 series devices. disabling a given peripheral minimizes its power consumption. power control register definitions the following sections describe the power control registers. power control register 0 each bit of the following registers disables a peripheral block, either by gating its system clock input or by removing power from the block.
ps024314-0308 low-power modes z8 encore! xp ? f0823 series product specification 33 this register is only reset during a power-on reset sequence. othe r system reset events do not affect it. reserved?must be 1 reserved?must be 0 vbo?voltage brownout detector disable this bit and the vbo_ao flas h option bit must both enable the vbo for the vbo to be active. 0 = vbo enabled 1 = vbo disabled adc?analog-to-digital converter disable 0 = analog-to-digital converter enabled 1 = analog-to-digital converter disabled comp?comparator disable 0 = comparator is enabled 1 = comparator is disabled reserved?must be 0 table 13. power control register 0 (pwrctl0) bits 7 6 5 4 3 2 1 0 field reserved reserved vbo reserved adc comp reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f80h note:
ps024314-0308 low-power modes z8 encore! xp ? f0823 series product specification 34
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 35 general-purpose input/output z8 encore! xp ? f0823 series products support a maximum of 24 port pins (ports a?c) for general-purpose input/output (gpio) opera tions. each port contains control and data registers. the gpio control registers determin e data direction, open-drain, output drive current, programmable pull-ups, stop mode recovery functionality, and alternate pin functions. each port pin is individually prog rammable. in addition, the port c pins are capable of direct led drive at programmable drive strengths. gpio port availability by device table 14 lists the port pins available w ith each device and package type. table 14. port availability by device and package type devices package 10-bit adc port a port b port c total i/o z8f0823sb, z8f0823pb z8f0423sb, z8f0423pb z8f0223sb, z8f0223pb z8f0123sb, z8f0123pb 8-pin yes [5:0] no no 6 z8f0813sb, z8f0813pb z8f0413sb, z8f0413pb z8f0213sb, z8f0213pb z8f0113sb, z8f011vpb 8-pin no [5:0] no no 6 z8f0823ph, z8f0823hh z8f0423ph, z8f0423hh z8f0223ph, z8f0223hh z8f0123ph, z8f0123hh 20-pin yes [7:0] [3:0] [3:0] 16 z8f0813ph, z8f0813hh z8f0413ph, z8f0413hh z8f0213ph, z8f0213hh z8f0113ph, z8f0113hh 20-pin no [7:0] [3:0] [3:0] 16 z8f0823pj, z8f0823sj z8f0423pj, z8f0423sj z8f0223pj, z8f0223sj z8f0123pj, z8f0123sj 28-pin yes [7:0] [5:0] [7:0] 22 z8f0813pj, z8f0813sj z8f0413pj, z8f0413sj z8f0213pj, z8f0213sj z8f0113pj, z8f0113sj 28-pin no [7:0] [7:0] [7:0] 24
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 36 architecture figure 7 displays a simplified block diagram of a gpio port pin. in this figure, the ability to accommodate altern ate functions and variable port current drive strength is not displayed. figure 7. gpio port pin block diagram gpio alternate functions many of the gpio port pins are used fo r general-purpose i/o and access to on-chip peripheral functions such as the timers and serial communication de vices. the port a?d alternate function sub-registers configure these pins for either gpio or alternate function operation. when a pin is configured for alternate function, control of the port pin direction (input/output) is passed from the port a?d data direction registers to the alternate func- tion assigned to this pin. table 15 on page 39 lists the altern ate functions possible with each port pin. the alternate function associat ed at a pin is defined through alternate function sets sub-registers afs1 and afs2. the crystal oscillator fu nctionality is not controlled by th e gpio block. when the crystal oscillator is enabled in the os cillator control block, the gpio functionality of pa0 and pa1 is overridden. in that case, th ose pins function as input and output for the crystal oscillator. d q dq d q gnd vdd port output control port data direction port output data register port input data register port pin data bus system clock system clock schmitt-trigger
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 37 pa0 and pa6 contain two different timer fu nctions, a timer input and a complementary timer output. both of these fu nctions require the same gpio configuration, the selection between the two is based on the tim er mode. for more details, see timers on page 67. for pin with multiple alternate functions , it is recommended to write to the afs1 and afs2 sub-registers before e nabling the alternate function via the af sub-register. this prevents spurious transitions through unwanted alternate function modes. direct led drive the port c pins provide a current sinked output capable of driving an led without requiring an external resistor. the output si nks current at programmable levels of 3 ma, 7 ma, 13 ma, and 20 ma. this mode is enabled through the alternate function sub-register afs1 and is programmable th rough the led control registers. the led drive enable (leden) register turns on th e drivers. the led drive level (ledlvlh and ledlvll) registers select the sink current. for correct function, the led anode must be connected to v dd and the cathode to the gpio pin. using all port c pins in led dr ive mode with maximum current can result in excessive total current. for the maximum tota l current for the applicable package, see electrical characteristics on page 193. shared reset pin on the 8-pin product versions, the reset pin is shared with pa2, but the pin is not limited to output-only when in gpio mode. if pa2 on the 8-pin product is reconfigured as an input, take care that no external stimulus drives the pin low during any reset sequence. since pa2 returns to its reset alternate function during system resets, driving it low holds the chip in a reset state until the pin is released. shared debug pin on the 8-pin version of this device only, the debug pin shares function with the pa0 gpio pin. this pin performs as a general purpose input pin on power-up, but the debug logic monitors this pin during the reset sequence to determine if the unlock sequence occurs. if the unlock sequence is present, the debug func tion is unlocked and the pin no longer func- caution: caution:
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 38 tions as a gpio pin. if it is not present, the debug feature is disabled until/unless another reset event occurs. fo r more details, see on-chip debugger on page 151. crystal oscillator override for systems using a crystal oscillator, pa0 and pa1 are used to connect the crystal. when the crystal oscillator is enabled (see oscillator control register definitions on page 167), the gpio settings are overridden and pa0 and pa1 are disabled. 5 v tolerance all six i/o pins on the 8-pin devices are 5 v-tolerant, unless the programmable pull-ups are enabled. if the pull-ups are en abled and inputs higher than v dd are applied to these parts, excessive current flows through thos e pull-up devices and can damage the chip. in the 20- and 28-pin versions of this devi ce, any pin which shares functionality with an adc, crystal or comparator port is not 5 v-tolerant, including pa[1:0], pb[5:0], and pc[2:0]. all other signal pins are 5 v-to lerant, and can safely handle inputs higher than v dd even with the pull-ups enabled. external clock setup for systems using an external ttl drive, pb 3 is the clock source for 20- and 28-pin devices. in this case, configure pb3 for a lternate function clkin. write the oscillator control register (see oscillator control register definitions on page 167) such that the external oscillator is selected as the system clock. for 8-pin devices use pa1 instead of pb3. note:
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 39 table 15. port alternate function mapping (non 8-pin parts) port pin mnemonic alternate function description alternate function set register afs1 port a pa0 t0in/t0out * timer 0 input/timer 0 output complement n/a reserved pa1 t0out timer 0 output reserved pa2 de0 uart 0 driver enable reserved pa3 cts0 uart 0 clear to send reserved pa4 rxd0/irrx0 uart 0 / irda 0 receive data reserved pa5 txd0/irtx0 uart 0 / irda 0 transmit data reserved pa6 t1in/t1out * timer 1 input/timer 1 output complement reserved pa7 t1out timer 1 output reserved note: because there is only a single alternate function for each port a pin, the alternate function set registers are not implemented for port a. enabling alte rnate function selections as described in port a?c alternate function sub-registers automatically enables the associated alternate function. * whether pa0/pa6 take on the timer input or time r output complement function depends on the timer configuration as described in timer pin signal operation on page 79.
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 40 port b pb0 reserved afs1[0]: 0 ana0 adc analog input afs1[0]: 1 pb1 reserved afs1[1]: 0 ana1 adc analog input afs1[1]: 1 pb2 reserved afs1[2]: 0 ana2 adc analog input afs1[2]: 1 pb3 clkin external clock input afs1[3]: 0 ana3 adc analog input afs1[3]: 1 pb4 reserved afs1[4]: 0 ana7 adc analog input afs1[4]: 1 pb5 reserved afs1[5]: 0 vref* adc voltage re ference afs1[5]: 1 pb6 reserved afs1[6]: 0 reserved afs1[6]: 1 pb7 reserved afs1[7]: 0 reserved afs1[7]: 1 note: because there are at most two choices of alternate function for any pin of port b, the alternate function set register afs2 is implemented but not used to select the function. also, alternate function selection as described in port a?c alternate function sub-registers must also be enabled. * vref is available on pb5 in 28-pin products only. table 15. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 41 port c pc0 reserved afs1[0]: 0 ana4/cinp/led drive adc or comparator input, or led drive afs1[0]: 1 pc1 reserved afs1[1]: 0 ana5/cinn/ led drive adc or comparator input, or led drive afs1[1]: 1 pc2 reserved afs1[2]: 0 ana6/led/ vref* adc analog input or led drive or adc voltage reference afs1[2]: 1 pc3 cout comparator output afs1[3]: 0 led led drive afs1[3]: 1 pc4 reserved afs1[4]: 0 led led drive afs1[4]: 1 pc5 reserved afs1[5]: 0 led led drive afs1[5]: 1 pc6 reserved afs1[6]: 0 led led drive afs1[6]: 1 pc7 reserved afs1[7]: 0 led led drive afs1[7]: 1 note: because there are at most two choices of alternate function for any pin of port c, the alternate function set register afs2 is implemented but not used to select the function. also, alter nate function selection as described in port a?c alternate function sub-registers must also be enabled. * vref is available on pc2 in 20-pin parts only. table 15. port alternate function mapping (non 8-pin parts) (continued) port pin mnemonic alternate function description alternate function set register afs1
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 42 table 16. port alternate function mapping (8-pin parts) port pin mnemonic alternate function description alternate function select register afs1 alternate function select register afs2 port a pa0 t0in timer 0 input afs1[0]: 0 afs2[0]: 0 reserved afs1[0]: 0 afs2[0]: 1 reserved afs1[0]: 1 afs2[0]: 0 t0out timer 0 output complement afs1[0]: 1 afs2[0]: 1 pa1 t0out timer 0 output afs1[1]: 0 afs2[1]: 0 reserved afs1[1]: 0 afs2[1]: 1 clkin external clock input afs1[1]: 1 afs2[1]: 0 analog functions* adc analog in put/vref afs1[1]: 1 afs2[1]: 1 pa2 de0 uart 0 driver e nable afs1[2]: 0 afs2[2]: 0 reset external reset afs1[2]: 0 afs2[2]: 1 t1out timer 1 output afs1[2]: 1 afs2[2]: 0 reserved afs1[2]: 1 afs2[2]: 1 pa3 cts0 uart 0 clear to send afs1[3]: 0 afs2[3]: 0 cout comparator output afs1[3]: 0 afs2[3]: 1 t1in timer 1 input afs1[3]: 1 afs2[3]: 0 analog functions* adc analog input afs1[3]: 1 afs2[3]: 1 pa4 rxd0 uart 0 receive da ta afs1[4]: 0 afs2[4]: 0 reserved afs1[4]: 0 afs2[4]: 1 reserved afs1[4]: 1 afs2[4]: 0 analog functions* adc/comparator input (n) afs1[4]: 1 afs2[4]: 1 pa5 txd0 uart 0 transmit data afs1[5]: 0 afs2[5]: 0 t1out timer 1 output complement afs1[5]: 0 afs2[5]: 1 reserved afs1[5]: 1 afs2[5]: 0 analog functions* adc/comparator input (p) afs1[5]: 1 afs2[5]: 1 note: * analog functions include adc inputs, adc reference and comparator inputs. also, al ternate function selection as described in port a?c alternate fu nction sub-registers must be enabled.
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 43 gpio interrupts many of the gpio port pins are used as interrupt sources. some port pins are configured to generate an interrupt request on either the rising edge or falling edge of the pin input signal. other port pin interrupt sources generate an interrupt when any edge occurs (both rising and falling). for more information about interrupts using the gpio pins, see interrupt controller on page 53. gpio control register definitions four registers for each port provide access to gpio control, input data, and output data. table 17 lists these port registers. use the port a?d address and control registers together to provide access to sub-regist ers for port configuration and control. table 17. gpio port registers and sub-registers port register mnemonic port register name p x addr port a?c address register (selects sub-registers) p x ctl port a?c control register (p rovides access to sub-registers) p x in port a?c input data register p x out port a?c output data register port sub-register mnemonic port register name p x dd data direction p x af alternate function p x oc output control (open-drain) p x hde high drive enable p x smre stop mode recovery source enable p x pue pull-up enable pxafs1 alternate function set 1 pxafs2 alternate function set 2
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 44 port a?c address registers the port a?c address registers select the gp io port functionality accessible through the port a?c control registers. the port a?c address and control re gisters combine to provide access to all gpio port controls ( table 18 ). paddr[7:0]?port address the port address selects one of the sub-re gisters accessible through the port control register. port a?c control registers the port a?c control registers set the gp io port operation. the value in the corresponding port a?c addre ss register determines which su b-register is read from or written to by a port a?c control register transaction ( table 19 ). table 18. port a?c gpio address registers (p x addr) bits 7 6 5 4 3 2 1 0 field paddr[7:0] reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd0h, fd4h, fd8h paddr[7:0] port control sub-re gister accessible using the port a?c control registers 00h no function. provides some protection against accidental port reconfiguration. 01h data direction. 02h alternate function. 03h output control (open-drain). 04h high drive enable. 05h stop mode recove ry source enable. 06h pull-up enable. 07h alternate function set 1. 08h alternate function set 2. 09h?ffh no function.
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 45 pctl[7:0]?port control the port control register provides access to a ll sub-registers that configure the gpio port operation. port a?c data direction sub-registers the port a?c data direction sub-register is accessed through the port a?c control register by writing 01h to the port a?c address register ( table 20 ). dd[7:0]?data direction these bits control the direction of the ass ociated port pin. port alternate function operation overrides the data direction register setting. 0 = output. data in the port a?c output da ta register is driven onto the port pin. 1 = input. the port pin is sampled and the value written into the port a?c input data register. the output driver is tristated. port a?c alternate fu nction sub-registers the port a?c alternate function sub-register ( table 21 ) is accessed through the port a?c control register by writing 02h to the port a?c address regi ster. the port a?c alternate function sub-registers enable the alternate function selection on pins. if disabled, pins functions as gpio. if enabled, select one of four alternate functions using alternate function set subregisters 1 and 2 as described in the port a?c alternate function set 1 sub-registers on page 48 and port a?c alternate function set 2 sub-registers on table 19. port a?c control registers (p x ctl) bits 7 6 5 4 3 2 1 0 field pctl reset 00h r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd1h, fd5h, fd9h table 20. port a?c data direction sub-registers (pxdd) bits 7 6 5 4 3 2 1 0 field dd7 dd6 dd5 dd4 dd3 dd2 dd1 dd0 reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 01h in port a?c address register, access ible through the port a?c control register
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 46 page 49. see gpio alternate functions on page 36 to determine the alternate function associated with each port pin. do not enable alternate functions for gpio port pins for which there is no associated alternate function. failure to follow this guideline can result in unpredictable operation. af[7:0]?port alternate function enabled 0 = the port pin is in normal mode and the ddx bit in the port a?c data direction sub- register determines the direction of the pin. 1 = the alternate function se lected through alternate fu nction set sub-registers is enabled. port pin operation is co ntrolled by the alternate function. port a?c output control sub-registers the port a?c output control sub-register ( table 22 ) is accessed through the port a?c control register by writing 03h to the port a?c address regi ster. setting the bits in the port a?c output control sub-registers to 1 configures the specified port pins for open- drain operation. these sub-registers affect th e pins directly and, as a result, alternate functions are also affected. poc[7:0]?port output control these bits function independently of the a lternate function bit and always disable the drains if set to 1. table 21. port a?c alternate function sub-registers (pxaf) bits 7 6 5 4 3 2 1 0 field af7 af6 af5 af4 af3 af2 af1 af0 reset 00h (ports a?c); 04h (port a of 8-pin device) r/w r/w addr if 02h in port a?c address register, access ible through the port a?c control register table 22. port a?c output control sub-registers (pxoc) bits 7 6 5 4 3 2 1 0 field poc7 poc6 poc5 poc4 poc3 poc2 poc1 poc0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 03h in port a?c address register, access ible through the port a?c control register caution:
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 47 0 = the drains are enabled for any output mode (unless overridden by the alternate function). 1 = the drain of the associated pin is disabled (open-drain mode). port a?c high drive enable sub-registers the port a?c high drive enable sub-register ( table 23 ) is accessed through the port a?c control register by writing 04h to the port a?c address register. setting the bits in the port a?c high drive enable sub-registers to 1 configures the specified port pins for high current output drive operation. the port a?c high drive enable sub-register affects the pins directly and, as a result, a lternate functions are also affected. phde[7:0]?port high drive enabled. 0 = the port pin is configured fo r standard output current drive. 1 = the port pin is configured for high output current drive. port a?c stop mode recovery source enable sub-registers the port a?c stop mode recovery source enable sub-register ( table 24 ) is accessed through the port a?c cont rol register by writing 05h to the port a?c address register. setting the bits in the port a?c stop mode recovery source enable sub-registers to 1 configures the specified port pins as a stop mode recovery source. during stop mode, any logic transition on a port pin enabled as a stop mode recovery source initiates stop mode recovery. table 23. port a?c high drive enable sub-registers (pxhde) bits 7 6 5 4 3 2 1 0 field phde7 phde6 phde5 phde4 phde3 phde2 phde1 phde0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 04h in port a?c address register, access ible through the port a?c control register table 24. port a?c stop mode recovery source enable sub-registers (pxsmre) bits 7 6 5 4 3 2 1 0 field psmre7 psmre6 psmre5 psmre4 psmre3 psmre2 psmre1 psmre0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 05h in port a?c address register, access ible through the port a?c control register
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 48 psmre[7:0]?port stop mode recovery source enabled. 0 = the port pin is not configured as a stop mode recovery source. transitions on this pin during stop mode do not initiate stop mode recovery. 1 = the port pin is configured as a stop mo de recovery source. an y logic transition on this pin during stop mode initiates stop mode recovery. port a?c pull-up enable sub-registers the port a?c pull-up en able sub-register ( table 25 ) is accessed through the port a?c control register by writing 06h to the port a?c address regi ster. setting the bits in the port a?c pull-up enable sub-registers enable s a weak internal resi stive pull-up on the specified port pins. ppue[7:0]?port pull-up enabled 0 = the weak pull-up on the port pin is disabled. 1 = the weak pull-up on the port pin is enabled. port a?c alternate function set 1 sub-registers the port a?c alternate func tion set1 sub-register ( table 26 ) is accessed through the port a?c control register by writing 07h to the port a?c address register. the alternate function set 1 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register are defined in gpio alternate functions on page 36. alternate function selection on port pins must also be enabled as described in port a?c alternate function sub-registers on page 45 . table 25. port a?c pull-up enable sub-registers (pxpue) bits 7 6 5 4 3 2 1 0 field ppue7 ppue6 ppue5 ppue4 ppue3 ppue2 ppue1 ppue0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 06h in port a ? c address register, accessible through the port a ? c control register note:
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 49 pafs1[7:0]?port alternate function set to 1 0 = port alternate function selected as defined in table 14 (see gpio alternate functions on page 36). 1 = port alternate function selected as defined in table 14 (see gpio alternate functions on page 36). port a?c alternate function set 2 sub-registers the port a?c alternate function set 2 sub-register ( table 27 ) is accessed through the port a?c control register by writing 08h to the port a?c address register. the alternate function set 2 sub-registers selects the alternat e function available at a port pin. alternate functions selected by setting or clearing bits of this register is defined in table 14 in the section gpio alternate functions on page 36. pafs2[7:0]?port alternate function set 2 0 = port alternate function selected as defined in table 14 (see gpio alternate functions on page 36). 1 = port alternate function selected as defined in table 14 . port a?c input data registers reading from the port a?c input data registers ( table 28 ) returns the sampled values from the corresponding port pi ns. the port a?c input data registers are read-only. the value returned for any unused ports is 0. unused ports include those missing on the 8- and 28-pin packages, as well as those missing on the adc-enabled 28-pin packages. table 26. port a?c alternate function set 1 sub-registers (pxafs1) bits 7 6 5 4 3 2 1 0 field pafs17 pafs16 pafs15 pafs14 pafs13 pafs12 pafs11 pafs10 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 07h in port a?c address register, access ible through the port a?c control register table 27. port a?c alternate function set 2 sub-registers (pxafs2) bits 7 6 5 4 3 2 1 0 field pafs27 pafs26 pafs25 pafs24 pafs23 pafs22 pafs21 pafs20 reset 00h (all ports of 20/28 pin devices); 04h (port a of 8-pin device) r/w r/wr/wr/wr/wr/wr/wr/wr/w addr if 08h in port a?c address register, access ible through the port a?c control register
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 50 pin[7:0]?port input data sampled data from the corresponding port pin input. 0 = input data is logical 0 (low) 1 = input data is logical 1 (high) port a?c output data register the port a?c output data register ( table 29 ) controls the output data to the pins. pout[7:0]?port output data these bits contain the data to be driven to th e port pins. the values are only driven if the corresponding pin is configured as an output and the pin is not configured for alternate function operation. 0 = drive a logical 0 (low). 1 = drive a logical 1 (high). high value is not driven if the drain has been disabled by setting the corresponding port outp ut control register bit to 1. led drive enable register the led drive enable register ( table 30 ) activates the controlled cu rrent drive. the port c pin must first be enabled by setting the a lternate function register to select the led function. table 28. port a?c input data registers (pxin) bits 7 6 5 4 3 2 1 0 field pin7 pin6 pin5 pin4 pin3 pin2 pin1 pin0 reset xxxxxxxx r/w rrrrrrrr addr fd2h, fd6h, fdah table 29. port a?c output data register (p x out) bits 7 6 5 4 3 2 1 0 field pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fd3h, fd7h, fdbh
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 51 . leden[7:0]?led drive enable these bits determine which port c pins are connected to an internal current sink. 0 = tristate the port c pin. 1= connect controlled current sink to the port c pin. led drive level high register the led drive level registers contain tw o control bits for each port c pin ( table 31 ). these two bits select between four programmab le drive levels. each pin is individually programmable. ledlvlh[7:0]?led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma 01= 7 ma 10= 13 ma 11= 20 ma led drive level low register the led drive level registers contain tw o control bits for each port c pin ( table 32 ). these two bits select between four programmab le drive levels. each pin is individually programmable. table 30. led drive enable (leden) bits 7 6 5 4 3 2 1 0 field leden[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f82h table 31. led drive level high register (ledlvlh) bits 7 6 5 4 3 2 1 0 field ledlvlh[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f83h
ps024314-0308 general-purpose input/output z8 encore! xp ? f0823 series product specification 52 ledlvlh[7:0]?led level high bit {ledlvlh, ledlvll} select one of four programmable current drive levels for each port c pin. 00 = 3 ma 01 = 7 ma 10 = 13 ma 11 = 20 ma table 32. led drive level low register (ledlvll) bits 7 6 5 4 3 2 1 0 field ledlvll[7:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f84h
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 53 interrupt controller the interrupt controller on the z8 encore! xp ? f0823 series products prioritizes the interrupt requests from the on-chip peripheral s and the gpio port pins. the features of interrupt controller include: ? 20 unique interrupt vectors ? 12 gpio port pin interrupt sources (two are shared) ? 8 on-chip peripheral interrupt sources (two are shared) ? flexible gpio interrupts ? eight selectable rising and falling edge gpio interrupts ? four dual-edge interrupts ? three levels of individually programmable interrupt priority ? watchdog timer can be configur ed to generate an interrupt interrupt requests (irqs) allow peripheral devi ces to suspend cpu oper ation in an orderly manner and force the cpu to start an interrupt service routine (isr). usually this interrupt service routine is involved with the exchange of data, stat us information, or control information between the cpu an d the interrupting peripheral. when the service routine is completed, the cpu returns to the op eration from which it was interrupted. the ez8 cpu supports both vectored and polled interrupt handling. for polled interrupts, the interrupt controller has no effect on ope ration. for more info rmation on interrupt servicing by the ez8 cpu, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . interrupt vector listing table 33 lists all of the interrupts available in or der of priority. the interrupt vector is stored with the most-significant byte (msb) at the even program memory address and the least-significant byte (lsb) at the following odd program memory address. some port interrupts are not available on the 8- and 20-pin packages. the adc interrupt is unavailable on devices not containing an adc. note:
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 54 table 33. trap and interrupt vectors in order of priority priority program memory vector address interrupt or trap source highest 0002h reset (not an interrupt) 0004h watchdog timer (see watchdog timer on page 87) 003ah primary oscillator fa il trap (not an interrupt) 003ch watchdog timer oscillator fail tr ap (not an interrupt) 0006h illegal instruction trap (not an interrupt) 0008h reserved 000ah timer 1 000ch timer 0 000eh uart 0 receiver 0010h uart 0 transmitter 0012h reserved 0014h reserved 0016h adc 0018h port a pin 7, selectabl e rising or falling input edge 001ah port a pin 6, selectable rising or falling input edge or comparator output 001ch port a pin 5, selectabl e rising or falling input edge 001eh port a pin 4, selectabl e rising or falling input edge 0020h port a pin 3 or port d pin 3, se lectable rising or falling input edge 0022h port a pin 2 or port d pin 2, se lectable rising or falling input edge 0024h port a pin 1, selectabl e rising or falling input edge 0026h port a pin 0, selectabl e rising or falling input edge 0028h reserved 002ah reserved 002ch reserved 002eh reserved 0030h port c pin 3, both input edges 0032h port c pin 2, both input edges 0034h port c pin 1, both input edges
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 55 architecture figure 8 displays the interrupt controller block diagram. figure 8. interrupt controller block diagram operation master interrupt enable the master interrupt enable bit ( irqe ) in the interrupt control register globally enables and disables interrupts. interrupts are globally enabled by any of the following actions: ? execution of an enable interrupt (ei) instruction ? execution of an return from interrupt ( iret ) instruction lowest 0036h port c pin 0, both input edges 0038h reserved table 33. trap and interrupt vectors in order of priority (continued) priority program memory vector address interrupt or trap source vector irq request high priority medium priority low priority priority mux interrupt request latches and control port interrupts internal interrupts
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 56 ? writing a 1 to the irqe bit in the interrupt control register interrupts are globally disabled by any of the following actions: ? execution of a disable interrupt (di ) instruction ? ez8 cpu acknowledgement of an interrupt se rvice request from the interrupt controller ? writing a 0 to the irqe bit in the interrupt control register ? reset ? execution of a trap instruction ? illegal instruction trap ? primary oscillator fail trap ? watchdog timer oscillator fail trap interrupt vectors and priority the interrupt controller supports three levels of interrupt pr iority. level 3 is the highest priority, level 2 is the second highest prior ity, and level 1 is the lowest priority. if all interrupts are enabled with identical interru pt priority (for example, all as level 2 interrupts), the interrupt priority is assign ed from highest to lowest as specified in table 33 on page 54. level 3 interrupts are always assigned higher priority than level 2 interrupts which, in turn, always are assigned higher pr iority than level 1 interrupts. within each interrupt priority level (level 1, level 2, or level 3), priority is ass igned as specified in table 33 . reset, watchdog timer interrupt (if enabled), primary oscillator fail trap, watchdog timer oscillator fa il trap, and illegal instruction trap always have highest (level 3) priority. interrupt assertion interrupt sources assert their interrupt requests for only a single system clock period (single pulse). when the interrupt request is acknowledged by the ez8 cpu, the corresponding bit in the interrupt request re gister is cleared until the next interrupt occurs. writing a 0 to the corresponding bit in the interrupt request register likewise clears the interrupt request. the following coding style that clears bits in the interru pt request registers is not recommended. all incoming interrupts received between execution of the first ldx command and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 and r0, mask ldx irq0, r0 caution:
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 57 to avoid missing interrupts, use the following coding style to clear bits in the interrupt request 0 register: good coding style that avoids lost interrupt requests: andx irq0, mask software interrupt assertion program code generates interrupts directly. wr iting a 1 to the correct bit in the interrupt request register triggers an interrupt (assumi ng that interrupt is enabled). when the inter- rupt request is acknowledged by the ez8 cpu, the bit in the interrupt request register is automatically cleared to 0. the following coding style used to generate software interrupts by setting bits in the interrupt request registers is not recomme nded. all incoming interrupts received between execution of the first ldx comma nd and the final ldx command are lost. poor coding style that can result in lost interrupt requests: ldx r0, irq0 or r0, mask ldx irq0, r0 to avoid missing interrupts, use the following coding style to set bits in the interrupt request registers: good coding style that avoi ds lost interrupt requests: orx irq0, mask watchdog timer interrupt assertion the watchdog timer interrupt behavior is different from interrupts generated by other sources. the watchdog timer continues to ass ert an interrupt as long as the timeout condi- tion continues. as it operates on a different (and usually slower) clock domain than the rest of the device, the watchdog timer contin ues to assert this interrupt for many system clocks until the counter rolls over. to avoid re-triggerings of the watchdog timer interrupt after exiting the associated in- terrupt service routine, it is recommended that the service routine co ntinues to read from the rststat register until the wdt bit is cleared as given in the following coding sample: clearwdt: ldx r0, rststat ; read reset status register to clear wdt bit btjnz 5, r0, clearwdt ; loop until bit is cleared caution: caution: caution: caution:
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 58 interrupt control re gister definitions for all interrupts other than the watchdog timer interrupt, the primary oscillator fail trap, and the watchdog timer oscillator fail trap, the interru pt control registers enable individual interrupts, set interrupt prio rities, and indicate interrupt requests. interrupt request 0 register the interrupt request 0 (irq0) register ( table 34 ) stores the interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq0 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu reads the interrupt request 0 register to determine if any interrupt requests are pending. reserved?must be 0 t1i?timer 1 interrupt request 0 = no interrupt request is pending for timer 1 1 = an interrupt request from timer 1 is awaiting service t0i?timer 0 interrupt request 0 = no interrupt request is pending for timer 0 1 = an interrupt request from timer 0 is awaiting service u0rxi?uart 0 receiver interrupt request 0 = no interrupt request is pe nding for the uart 0 receiver 1 = an interrupt request from the ua rt 0 receiver is awaiting service u0txi?uart 0 transmitter interrupt request 0 = no interrupt request is pending for the uart 0 transmitter 1 = an interrupt request from the ua rt 0 transmitter is awaiting service adci?adc interrupt request 0 = no interrupt request is pending for the adc 1 = an interrupt request from the adc is awaiting service table 34. interrupt request 0 register (irq0) bits 7 6 5 4 3 2 1 0 field reserved t1i t0i u0rxi u0txi reserved reserved adci reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc0h
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 59 interrupt request 1 register the interrupt request 1 (irq1) register ( table 35 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq1 register be comes 1. if interrupts are globally enabled (vectored interrupts), the interrupt controller pa sses an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu reads the interrupt request 1 register to determine if any interrupt requests are pending. pa7vi?port a7 interrupt request 0 = no interrupt request is pending for gpio port a 1 = an interrupt request from gpio port a pa6ci?port a6 or comparator interrupt request 0 = no interrupt request is pendin g for gpio port a or comparator 1 = an interrupt request from gpio port a or comparator pa x i?port a pin x interrupt request 0 = no interrupt request is pending for gpio port a pin x 1 = an interrupt request from gpio port a pin x is awaiting service where x indicates the specific gpio port pin number (0?5) interrupt request 2 register the interrupt request 2 (irq2) register ( table 36 ) stores interrupt requests for both vectored and polled interrupts. when a request is presented to the in terrupt controller, the corresponding bit in the irq2 register beco mes 1. if interrupts are globally enabled (vec- tored interrupts), the interrupt controller passe s an interrupt request to the ez8 cpu. if interrupts are globally disabl ed (polled interrupts), the ez8 cpu can read the interrupt request 2 register to determine if any interrupt requests are pending. table 35. interrupt request 1 register (irq1) bits 7 6 5 4 3 2 1 0 field pa7vi pa6ci pa5i pa4i pa3i pa2i pa1i pa0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc3h
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 60 reserved?must be 0 pc x i?port c pin x interrupt request 0 = no interrupt request is pending for gpio port c pin x 1 = an interrupt request from gpio port c pin x is awaiting service where x indicates the specific gpio port c pin number (0?3) irq0 enable high and low bit registers table 37 describes the priority control for ir q0. the irq0 enable high and low bit registers ( table 38 and table 39 ) form a priority encoded en abling for interrupts in the interrupt request 0 register. priority is generated by se tting bits in each register. table 36. interrupt request 2 register (irq2) bits 7 6 5 4 3 2 1 0 field reserved pc3i pc2i pc1i pc0i reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc6h table 37. irq0 enable and priority encoding irq0enh[ x ] irq0enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 1 1 level 3 high where x indicates the register bits from 0?7. table 38. irq0 enable high bit register (irq0enh) bits 7 6 5 4 3 2 1 0 field reserved t1enh t0enh u0renh u0tenh reserved reserved adcenh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc1h
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 61 reserved?must be 0 t1enh?timer 1 interrupt re quest enable high bit t0enh?timer 0 interrupt re quest enable high bit u0renh?uart 0 receive interrupt request enable high bit u0tenh?uart 0 transmit interrupt request enable high bit adcenh?adc interrupt request enable high bit reserved?0 when read t1enl?timer 1 interrupt request enable low bit t0enl?timer 0 interrupt request enable low bit u0renl?uart 0 receive interru pt request enable low bit u0tenl?uart 0 transmit interrupt request enable low bit adcenl?adc interrupt request enable low bit irq1 enable high and low bit registers table 40 describes the priority control for ir q1. the irq1 enable high and low bit registers ( table 41 and table 42 ) form a priority encoded en abling for interrupts in the interrupt request 1 register. priority is generated by se tting bits in each register. table 39. irq0 enable low bit register (irq0enl) bits 7 6 5 4 3 2 1 0 field reserved t1enl t0enl u0renl u0 tenl reserved reserved adcenl reset 00000000 r/w r r/w r/w r/w r/w r r r/w addr fc2h table 40. irq1 enable and priority encoding irq1enh[ x ]irq1enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal 11 level 3 high where x indicates the register bits from 0?7.
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 62 pa7venh?port a bit[7] interrupt request enable high bit pa6cenh?port a bit[7] or comparator interrupt request enable high bit pa x enh?port a bit[ x ] interrupt request enable high bit for selection of port a as the interrupt source, see shared interrupt select register on page 64. pa7venh?port a bit[7] interru pt request enable low bit pa6cenh?port a bit[6] or comparator interrupt request enable low bit pa x enl?port a bit[ x ] interrupt reques t enable low bit irq2 enable high and low bit registers table 43 describes the priority control for ir q2. the irq2 enable high and low bit registers ( table 44 and table 45 ) form a priority encoded en abling for interrupts in the interrupt request 2 register. priority is generated by se tting bits in each register. table 41. irq1 enable high bit register (irq1enh) bits 7 6 5 4 3 2 1 0 field pa7venh pa6cenh pa5enh pa4enh pa3enh pa2enh pa1enh pa0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc4h table 42. irq1 enable low bit register (irq1enl) bits 7 6 5 4 3 2 1 0 field pa7venl pa6cenl pa5enl pa4enl pa3enl pa2enl pa1enl pa0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc5h table 43. irq2 enable and priority encoding irq2enh[ x ]irq2enl[ x ] priority description 0 0 disabled disabled 0 1 level 1 low 1 0 level 2 nominal
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 63 reserved?must be 0 c3enh?port c3 interrupt request enable high bit c2enh?port c2 interrupt request enable high bit c1enh?port c1 interrupt request enable high bit c0enh?port c0 interrupt request enable high bit reserved?must be 0 c3enl?port c3 interrupt request enable low bit c2enl?port c2 interrupt request enable low bit c1enl?port c1 interrupt request enable low bit c0enl?port c0 interrupt request enable low bit interrupt edge select register the interrupt edge sele ct (irqes) register ( table 46 ) determines whether an interrupt is generated for the rising edge or falling edge on the selected gpio port a or port d input pin. 1 1 level 3 high where x indicates the register bits from 0?7. table 44. irq2 enable high bit register (irq2enh) bits 7 6 5 4 3 2 1 0 field reserved c3enh c2enh c1enh c0enh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc7h table 45. irq2 enable low bit register (irq2enl) bits 7 6 5 4 3 2 1 0 field reserved c3enl c2enl c1enl c0enl reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fc8h table 43. irq2 enable and priority encoding (continued) irq2enh[ x ]irq2enl[ x ] priority description
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 64 ies x ?interrupt edge select x 0 = an interrupt request is genera ted on the falling edge of the pa x input or pdx 1 = an interrupt request is genera ted on the rising edge of the pa x input pdx where x indicates the specific gpio port pin number (0 through 7) shared interrupt select register the shared interrupt select (irqss) register ( table 47 ) determines the source of the padxs interrupts. the shared interrupt sele ct register selects between port a and alternate sources for the individual interrupts. because these shared interrupts are edge-trigger ed, it is possible to generate an interrupt just by switching from one shared source to another. for this reason, an interrupt must be disabled before switching between sources. pa6cs?pa6/comparator selection 0 = pa6 is used for the interru pt for pa6cs interrupt request 1 = the comparator is used for the interrupt for pa6cs interrupt request reserved?must be 0 interrupt control register the interrupt control (irqctl) register ( table 48 ) contains the master enable bit for all interrupts. table 46. interrupt edge select register (irqes) bits 7 6 5 4 3 2 1 0 field ies7 ies6 ies5 ies4 ies3 ies2 ies1 ies0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fcdh table 47. shared interrupt select register (irqss) bits 7 6 5 4 3 2 1 0 field reserved pa6cs reserved reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr fceh
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 65 irqe?interrupt request enable this bit is set to 1 by executing an ei (enable interrupts) or iret (interrupt return) instruction, or by a direct register write of a 1 to this bit. it is reset to 0 by executing a di instruction, ez8 cpu acknowledgement of an inte rrupt request, reset or by a direct register write of a 0 to this bit. 0 = interrupts are disabled 1 = interrupts are enabled reserved?0 when read table 48. interrupt control register (irqctl) bits 7 6 5 4 3 2 1 0 field irqe reserved reset 00000000 r/w r/wrrrrrrr addr fcfh
ps024314-0308 interrupt controller z8 encore! xp ? f0823 series product specification 66
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 67 timers z8 encore! xp ? f0823 series products contain up to two 16-bit reloadable timers that are used for timing, event counting, or generation of pwm signals. the timers? features include: ? 16-bit reload counter. ? programmable prescaler with pres cale values from 1 to 128. ? pwm output generation. ? capture and compare capability. ? external input pin for timer input, clock gating, or capture signal. external input pin signal frequency is limited to a maximum of on e-fourth the system clock frequency. ? timer output pin. ? timer interrupt. in addition to the timers described in this ch apter, the baud rate ge nerator of the uart (if unused) also provides basic ti ming functionality. for informa tion on using the baud rate generator as an ad ditional timer, see universal asynchronous receiver/transmitter on page 93. architecture figure 9 displays the architecture of the timers. figure 9. timer block diagram 16-bit pwm/compare 16-bit counter with prescaler 16-bit reload register timer control compare compare interrupt, pwm, and timer output control timer timer block system timer data block output control bus clock input gate input capture input timer interrupt timer output complement timer output complement
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 68 operation the timers are 16-bit up-counters. minimum tim e-out delay is set by loading the value 0001h into the timer reload high and low by te registers and setting the prescale value to 1. maximum time-out delay is set by loading the value 0000h into the timer reload high and low byte registers and setting the prescale value to 128. if the timer reaches ffffh , the timer rolls over to 0000h and continues counting. timer operating modes the timers can be configured to operate in the following modes: one-shot mode in one-shot mode, the timer counts up to th e 16-bit reload value stored in the timer reload high and low byte registers. the timer input is the system clock. upon reaching the reload value, the timer generates an interrupt and th e count value in the timer high and low byte registers is reset to 0001h . the timer is automatically disabled and stops counting. also, if the timer output alternate function is enabled, the timer output pin changes state for one system clock cycle (from low to high or from high to low) upon timer reload. if it is appropriate to have the timer output ma ke a state change at a one-shot time-out (rather than a single cycle pulse), first set the tpol bit in the timer control register to the start value before enabling one-shot mode. after starting the timer, set tpol to the opposite bit value. follow the steps below for configuring a timer for one-shot mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for one-shot mode ? set the prescale value ? set the initial output level (high or lo w) if using the timer output alternate function 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function.
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 69 6. write to the timer control register to enable the timer and initiate counting. in one-shot mode, the system clock always provides the timer input. the timer period is given by the following equation: continuous mode in continuous mode, the timer counts up to the 16-bit reload va lue stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the reload value, the timer generate s an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate func tion is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below to configure a timer for continuous mode and to initiate the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for continuous mode ? set the prescale value ? if using the timer output alternate functio n, set the initial output level (high or low) 2. write to the timer high and low byte regist ers to set the starting count value (usually 0001h ). this action only affects the first p ass in continuous mode. after the first timer reload in continuous mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt (if appropriate ) and set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pin (i f using the timer output function) for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in continuous mode, the system clock alwa ys provides the timer input. the timer period is given by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equatio n to determine the first time-out period. one-shot mode time-out period (s) reload value start value ? () prescale system clock frequency (hz) ----------------------------------------------------------------------------------------------- = continuous mode time-out period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 70 counter mode in counter mode, the timer co unts input transitions from a gpio port pin. the timer input is taken from the gpio port pi n timer input alternate function. the tpol bit in the timer control register selects whether the c ount occurs on the rising edge or the falling edge of the timer input signal. in co unter mode, the prescaler is disabled. the input frequency of the timer input si gnal must not exceed one-fourth the system clock frequency. upon reaching the reload value stored in the timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below for configuring a timer for counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for counter mode. ? select either the rising edge or falling edge of the timer input signal for the count. this selection also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this only affects the first pass in counter mode. after the first timer reload in counter mode, counting always begins at the reset value of 0001h . in counter mode the timer high and low byte regi sters must be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. configure the associated gpio port pi n for the timer input alternate function. 6. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer. in counter mode, the number of timer input transitions since the timer start is given by the following equation: caution: counter mode timer input transitions current count value start value ? =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 71 comparator counter mode in comparator counter mode , the timer counts input tr ansitions from the analog comparator output. the tpol bit in the timer control register selects whether the count occurs on the rising edge or the falling edge of the comparator output signal. in comparator counter mode, the prescaler is disabled. the frequency of the comparator output si gnal must not exceed one-fourth the system clock frequency. after reaching the reload value stored in th e timer reload high and low byte registers, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) at timer reload. follow the steps below for configuring a timer for comparator counter mode and initiating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for co mparator counter mode. ? select either the rising edge or falling edge of the comparator output signal for the count. this also sets the initial logic le vel (high or low) for the timer output alternate function. however, the timer ou tput function is not required to be enabled. 2. write to the timer high and low byte regi sters to set the startin g count value. this action only affects the first pass in co mparator counter mode. after the first timer reload in comparator counter mode, counting always begins at the reset value of 0001h . generally, in comparator counter mode the timer high and low byte registers mu st be written with the value 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer. in comparator counter mode, the number of comparator output transitions since the timer start is given by the following equation: caution: comparator output transitions current count value start value ? =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 72 pwm single output mode in pwm single output mode, the timer outputs a pwm output signal through a gpio port pin. the timer input is the system cl ock. the timer first counts up to the 16-bit pwm match value stored in the timer pwm high and low byte registers. when the timer count value matches the pwm value, th e timer output toggles. the timer continues counting until it reaches the reload value stor ed in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . follow the steps below for configuring a timer for pwm single output mode and initiat- ing the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm mode ? set the prescale value ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 5. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 6. configure the associated gpio port pin for the timer output alternate function. 7. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: pwm period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 73 if an initial starting value other than 0001h is loaded into the timer high and low byte registers, use the one-shot mode equation to determine the first pwm time-out period. if tpol is set to 0, the ratio of the pwm ou tput high time to the total period is represented by the following equation: if tpol is set to 1, the ratio of the pwm ou tput high time to the total period is represented by the following equation: pwm dual output mode in pwm dual output mode, the timer output s a pwm output signal pair (basic pwm signal and its complement) through two gpio port pins. the timer input is the system clock. the timer first counts up to the 16 -bit pwm match value stored in the timer pwm high and low byte registers. when the ti mer count value matches the pwm value, the timer output toggles. the timer continues counting until it reach es the reload value stored in the timer reload high and low byte registers. upon reaching the reload value, the timer generates an interrupt, the count value in the ti mer high and low byte registers is reset to 0001h and counting resumes. if the tpol bit in the timer control register is set to 1, the timer output signal begins as a high (1) and transitions to a low (0) when the timer value match es the pwm value. the timer output signal returns to a high (1) after the timer re aches the reload value and is reset to 0001h . if the tpol bit in the timer control register is set to 0, the timer output signal begins as a low (0) and transitions to a high (1) when the timer value match es the pwm value. the timer output signal returns to a low (0) after the timer reaches the reload value and is reset to 0001h . the timer also generates a second pwm outp ut signal timer output complement. the timer output complement is the compleme nt of the timer output pwm signal. a programmable deadband delay can be configured to time delay (0 to 128 system clock cycles) pwm output transitions on these two pins from a low to a high (inactive to active). this ensures a time gap between the deassertion of one pwm output to the assertion of its complement. follow the steps below for conf iguring a timer for pwm dual output mode and initiating the pwm operation: 1. write to the timer control register to: ? disable the timer ? configure the timer for pwm dual output mode. setting the mode also involves writing to tmodehi bit in txctl1 register ? set the prescale value pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------- 100 = pwm output high time ratio (%) pwm value reload value ----------------------------------- - 100 =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 74 ? set the initial logic level (high or lo w) and pwm high/low transition for the timer output alternate function 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). this only affects the first pass in pwm mode. after the first timer reset in pwm mode, counting always begins at the reset value of 0001h . 3. write to the pwm high and low byte registers to set the pwm value. 4. write to the pwm control register to set the pwm dead band delay value. the deadband delay must be less th an the duration of the pos itive phase of the pwm signal (as defined by the pwm high and low byte re gisters). it must also be less than the duration of the negative phase of the pw m signal (as defined by the difference between the pwm registers and the timer reload registers). 5. write to the timer reload high and low by te registers to set the reload value (pwm period). the reload value must be greater than the pwm value. 6. if appropriate, enable the timer interrupt an d set the timer interrupt priority by writing to the relevant interrupt registers. 7. configure the associated gpio port pin for the timer output and timer output complement alternate functio ns. the timer output comple ment function is shared with the timer input function for both tim ers. setting the timer mode to dual pwm automatically switches the function from timer in to timer out complement. 8. write to the timer control register to enable the timer and initiate counting. the pwm period is represented by the following equation: if an initial starting value other than 0001h is loaded into the timer high and low byte registers, the one-shot mode equation determines the first pwm time-out period. if tpol is set to 0, the ratio of the pwm outp ut high time to the total period is repre- sented by: if tpol is set to 1, the ratio of the pwm outp ut high time to the total period is repre- sented by: capture mode in capture mode, the current timer count valu e is recorded when the appropriate exter- nal timer input transition occu rs. the capture count value is written to the timer pwm high and low byte registers. the tim er input is the system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge pwm period (s) reload value prescale system clock frequency (hz) ------------------------------------------------------------------------ = pwm output high time ratio (%) reload value pwm value ? reload value ------------------------------------------------------------------ - 100 = pwm output high time ratio (%) pwm value reload value ----------------------------------- - 100 =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 75 of the timer input signal. when the capture ev ent occurs, an interrupt is generated and the timer continues counting. the inpcap bit in txctl1 register is set to indicate the timer interrupt is because of an input capture event. the timer continues coun ting up to the 16-bit reload valu e stored in the timer reload high and low byte registers. upon reaching the reload va lue, the timer generates an interrupt and continues counting. the inpcap bit in txctl1 register clears indicating the timer interrupt is not because of an input capture event. follow the steps below for configuring a timer for capture mode and initiating the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for capture mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . clearing these registers allows the software to determin e if interrupts were generated by either a capture or a reload event. if the pwm hi gh and low byte registers still contain 0000h after the interrupt, the interru pt was generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload even ts. if appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: capture restart mode in capture restart mode, the current ti mer count value is recorded when the acceptable external timer input transition oc curs. the capture count value is written to the timer pwm high and low byte registers. the timer input is th e system clock. the tpol bit in the timer control register determines if the capture occurs on a rising edge or a falling edge of the timer input signal. when the capture event occurs, an interrupt is capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------- - =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 76 generated and the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is set to indicate the timer interrupt is because of an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the reload value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is cleared to indicate the timer interrupt is not cause d by an input capture event. follow the steps below for configuring a timer for capture restart mode and initi- ating the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for capture re start mode. setting the mode also involves writing to tmodehi bit in txctl1 register. ? set the prescale value. ? set the capture edge (rising or falling) for the timer input. 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the reload value. 4. clear the timer pwm high and low byte registers to 0000h . this allows the software to determine if interrupts were ge nerated by either a capture or a reload event. if the pwm high and low byte registers still contain 0000h after the interrupt, the interrupt was generated by a reload. 5. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input capture and reload even ts. if appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 6. configure the associated gpio port pi n for the timer input alternate function. 7. write to the timer control register to enable the timer and initiate counting. in capture mode, the elapsed time from timer start to capture event can be calculated using the following equation: compare mode in compare mode, the timer counts up to the 16-bit maximum compare value stored in the timer reload high and low byte registers. the timer input is th e system clock. upon reaching the compare value, the timer genera tes an interrupt and co unting continues (the capture elapsed time (s) capture value start value ? () prescale system clock frequency (hz) ------------------------------------------------------------------------------------------------- - =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 77 timer value is not reset to 0001h ). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from high to low) upon compare. if the timer reaches ffffh , the timer rolls over to 0000h and continue counting. follow the steps below to configure a timer for compare mode and to initiate the count: 1. write to the timer control register to: ? disable the timer. ? configure the timer for compare mode. ? set the prescale value. ? set the initial logic level (high or low) fo r the timer output alternate function, if appropriate. 2. write to the timer high and low byte registers to set the starting count value. 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers. 5. if using the timer output function, configure the associated gpio port pin for the timer output alternate function. 6. write to the timer control register to enable the timer and initiate counting. in compare mode, the system clock always pr ovides the timer inpu t. the compare time can be calculated by the following equation: gated mode in gated mode, the timer counts only when the timer input si gnal is in its active state (asserted), as determined by the tpol bit in the timer control register. when the timer input signal is asserted, counting begins. a timer interrupt is generated when the timer input signal is deasserted or a timer reload occurs. to determine if a timer input signal deassertion generated the interrupt, read the as sociated gpio input value and compare to the value stored in the tpol bit. the timer counts up to the 16 -bit reload value stored in th e timer reload high and low byte registers. the timer input is the system clock. when r eaching the relo ad value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes (assuming the ti mer input signal remains asserted). also, if the timer output alternate function is enabled, the timer output pin changes state (from low to high or from hi gh to low) at timer reset. compare mode time (s) compare value start value ? () prescale system clock frequency (hz) ---------------------------------------------------------------------------------------------------- - =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 78 follow the steps below to configure a timer for gated mode and to initiate the count: 1. write to the timer control register to: ? disable the timer ? configure the timer for gated mode ? set the prescale value 2. write to the timer high and low byte regist ers to set the starting count value. writing these registers only affects the first pass in gated mode. after the first timer reset in gated mode, counting always begins at the reset value of 0001h . 3. write to the timer reload high and low byte registers to set the reload value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt regist ers. by default, the timer in terrupt is generated for both input deassertion and reload events. if appropri ate, configure the tim er interrupt to be generated only at the input deassertion event or the reload event by setting ticonfig field of the txctl1 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. assert the timer input signal to initiate the counting. capture/compare mode in capture/compare mode, the timer begins counting on the first external timer input transition. the acceptable transition (ri sing edge or falling edge) is set by the tpol bit in the timer control register. th e timer input is th e system clock. every subsequent acceptable transition (after the first) of the timer input signal captures the current count value. the capture valu e is written to the timer pwm high and low byte registers. when the capt ure event occurs, an interrupt is generated, the count value in the timer high and low byte registers is reset to 0001h , and counting resumes. the inpcap bit in txctl1 register is set to indicat e the timer interrupt is caused by an input capture event. if no capture event occurs, the timer counts up to the 16-bit compare value stored in the timer reload high and low byte registers. up on reaching the compare value, the timer generates an interrupt, the count value in the timer high and low byte registers is reset to 0001h and counting resumes. the inpcap bit in txctl1 register is cleared to indicate the timer interrupt is not becau se of an input capture event. follow the steps below for configuring a timer for capture/compare mode and initi- ating the count: 1. write to the timer control register to: ? disable the timer
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 79 ? configure the timer for capture/compare mode ? set the prescale value ? set the capture edge (rising or falling) for the timer input 2. write to the timer high and low byte registers to set the starting count value (typically 0001h ). 3. write to the timer reload high and low byte registers to set the compare value. 4. enable the timer interrupt, if appropriate, and set the timer interr upt priority by writing to the relevant interrupt registers.by defau lt, the timer interrupt are generated for both input capture and reload even ts. if appropriate, configure the timer interrupt to be generated only at the input capture event or the reload event by setting ticonfig field of the txctl1 register. 5. configure the associated gpio port pi n for the timer input alternate function. 6. write to the timer control register to enable the timer. 7. counting begins on the first appropriate transition of the timer input signal. no interrupt is generated by this first edge. in capture/compare mode, the elapsed time from timer start to capture event can be calculated using the following equation: reading the timer count values the current count va lue in the timers can be read while counting (enabled). this capability has no effect on timer operation. when th e timer is enabled and the timer high byte register is read, the contents of the time r low byte register are placed in a holding register. a subsequent read from the timer low byte register returns the value in the hold- ing register. this operation a llows accurate reads of the fu ll 16-bit timer count value while enabled. when the timers are not enabled, a read from the timer low byte register returns the actual value in the counter. timer pin signal operation timer output is a gpio port pin alternate function. the timer output is toggled every time the counter is reloaded. the timer input can be used as a selectable counting source. it shares the same pin as the complementary timer output. when selected by the gpio alternate function registers, this pin functions as a timer input in all modes except for the dual pwm output mode. for this mode, there is no timer input available. capture elapsed time (s) c ap t ure v a l ue st ar t v a l ue ? () p resca l e system clock frequency (hz) ----------------------------------------------------------------------------------------------------------------------- - =
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 80 timer control register definitions timer 0?1 high and low byte registers the timer 0?1 high and low byte (txh and txl) registers ( table 49 and table 50 ) contain the current 16-bit timer count value. when the timer is enabled, a read from txh causes the value in txl to be stored in a temporary holding register. a read from txl always returns this temporary register when the timers are enabled. when the timer is dis- abled, reads from the txl reads the register directly. writing to the timer high and low byte regist ers while the timer is enabled is not recom- mended. there are no temporary holding regist ers available for write operations, so simul- taneous 16-bit writes are not possible. if eith er the timer high or low byte registers are written during counting, the 8- bit written value is placed in the counter (high or low byte) at the next clock edge. the coun ter continues counting from the new value. th and tl?timer high and low bytes these 2 bytes, {th[7:0], tl[7:0]}, cont ain the current 16-b it timer count value timer reload high and low byte registers the timer 0?1 reload high and low byte (txrh and txrl) registers ( table 51 and table 52 ) store a 16-bit reload value, {trh[7:0], trl[7:0]}. values written to the timer reload high byte register are stored in a te mporary holding register. when a write to the timer reload low byte register occurs, the te mporary holding register value is written to the timer high byte register. this operation allows simultaneous updates of the 16-bit timer reload value. table 49. timer 0?1 high byte register (txh) bits 7 6 5 4 3 2 1 0 field th reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f00h, f08h table 50. timer 0?1 low byte register (txl) bits 7 6 5 4 3 2 1 0 field tl reset 00000001 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f01h, f09h
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 81 in compare mode, the timer reload high and low byte registers store the 16-bit compare value. trh and trl?timer reload register high and low these two bytes form the 16-bit reload value, {trh[7:0], trl[ 7:0]}. this value sets the maximum count valu e which initiates a timer reload to 0001h . in compare mode, these two bytes form the 16-bit compare value. timer 0-1 pwm high and low byte registers the timer 0-1 pwm high and low byte (txpwmh and txpwml) registers ( table 53 and table 54 ) control pulse-width modulator (pwm) op erations. these registers also store the capture values for the capture and capture/compare modes. table 51. timer 0?1 reload high byte register (txrh) bits 7 6 5 4 3 2 1 0 field trh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f02h, f0ah table 52. timer 0?1 reload low byte register (txrl) bits 7 6 5 4 3 2 1 0 field trl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f03h, f0bh table 53. timer 0?1 pwm high byte register (txpwmh) bits 7 6 5 4 3 2 1 0 field pwmh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f04h, f0ch
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 82 pwmh and pwml?pulse-width mo dulator high and low bytes these two bytes, {pwmh[7:0], pwml[7:0]}, form a 16-bit value that is compared to the current 16-bit timer count. when a match oc curs, the pwm output changes state. the pwm output value is set by the tpol bit in the timer control register (txctl1) register. the txpwmh and txpwml registers also st ore the 16-bit captured timer value when operating in capture or capture/compare modes. timer 0?1 control registers time 0?1 control register 0 the timer control register 0 (txctl0) and timer control register 1 (txctl1) determine the timer operating mode. it al so includes a programmable pwm deadband delay, two bits to configure ti mer interrupt definition, and a status bit to identify if the most recent timer interrupt is caused by an input capture event. tmodehi?timer mode high bit this bit along with the tmode field in txc tl1 register determines the operating mode of the timer. this is the most-significant bit of the timer mode selection value. see the txctl1 register description for more details. ticonfig?timer interrupt configuration this field configures timer interrupt definition. table 54. timer 0?1 pwm low byte register (txpwml) bits 7 6 5 4 3 2 1 0 field pwml reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f05h, f0dh table 55. timer 0?1 control register 0 (txctl0) bits 7 6 5 4 3 2 1 0 field tmodehi ticonfig reserved pwmd inpcap reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f06h, f0eh
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 83 0x = timer interrupt occurs on all de fined reload, compar e and input events 10 = timer interrupt only on defi ned input capture/deassertion events 11 = timer interrupt only on defined reload/compare events reserved?must be 0 pwmd?pwm delay value this field is a programmable delay to contro l the number of system clock cycles delay before the timer output and th e timer output complement are forced to their active state. 000 = no delay 001 = 2 cycles delay 010 = 4 cycles delay 011 = 8 cycles delay 100 = 16 cycles delay 101 = 32 cycles delay 110 = 64 cycles delay 111 = 128 cycles delay inpcap?input capture event this bit indicates if the most recent timer in terrupt is caused by a timer input capture event. 0 = previous timer interrupt is not a result of timer input capture event 1 = previous timer interrupt is a result of timer input capture event timer 0?1 control register 1 the timer 0?1 control (txctl1) registers en able/disable the timers, set the prescaler value, and determine the timer operating mode. ten?timer enable 0 = timer is disabled 1 = timer enabled to count tpol?timer input/output polarity operation of this bit is a function of the current operating mode of the timer table 56. timer 0?1 control register 1 (txctl1) bits 7 6 5 4 3 2 1 0 field ten tpol pres tmode reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f07h, f0fh
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 84 one-shot mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. continuous mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. counter mode if the timer is enabled the timer output si gnal is complemented after timer reload. 0 = count occurs on the rising edge of the timer input signal 1 = count occurs on the falling ed ge of the timer input signal pwm single output mode 0 = timer output is forced low (0) when the timer is disabled. when enabled, the timer output is forced hi gh (1) upon pwm count matc h and forced low (0) upon reload. 1 = timer output is forced high (1) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload. capture mode 0 = count is captured on the rising edge of the timer input signal 1 = count is captured on the fallin g edge of the timer input signal compare mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. gated mode 0 = timer counts when the timer input signal is high (1) and interrupts are generated on the falling edge of the timer input. 1 = timer counts when the ti mer input signal is low (0) and interrupts are generated on the rising edge of the timer input.
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 85 capture/compare mode 0 = counting is started on the first rising edge of the timer input signal. the current count is captured on subsequent risi ng edges of the timer input signal. 1 = counting is started on the first falling ed ge of the timer input signal. the current count is captured on subsequent fa lling edges of the timer input signal. pwm dual output mode 0 = timer output is forced low (0) and time r output complement is forced high (1) when the timer is disabled. when enabled, the timer output is forced high (1) upon pwm count match and forced low (0) upon reload. when enabled, the timer output complement is forced low (0) upon pwm count match an d forced high (1) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before th e timer output and the timer output complement is fo rced to high (1). 1 = timer output is forced high (1) and ti mer output complement is forced low (0) when the timer is disabled. when enabled, the timer output is forced low (0) upon pwm count match and forced high (1) upon reload.when enabled, the timer output complement is forced high (1) upon p wm count match and forced low (0) upon reload. the pwmd field in txctl0 register is a programmable delay to control the number of cycles time delay before th e timer output and the timer output complement is fo rced to low (0). capture restart mode 0 = count is captured on the rising edge of the timer input signal 1 = count is captured on the fallin g edge of the timer input signal comparator counter mode when the timer is disabled, the timer output signal is set to the value of this bit. when the timer is enabled, the timer outp ut signal is complemented upon timer reload. when the timer output alternate function tx out on a gpio port pin is enabled, tx- out changes to whatever state the tpol bit is in. the timer does not need to be enabled for that to happen. also, the port data direction sub register is not needed to be set to output on txout. changing the tpol bit with the timer enabled and running does not immediately change the txout. pres?prescale value. the timer input clock is divided by 2 pres , where pres can be set from 0 to 7. the prescaler is reset each time the timer is disabled. this reset ensures proper clock division each time the timer is restarted. 000 = divide by 1 001 = divide by 2 caution:
ps024314-0308 timers z8 encore! xp ? f0823 series product specification 86 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = divide by 64 111 = divide by 128 tmode?timer mode this field along with the tmodehi bit in txctl0 register determines the operating mode of the timer. tmodehi is the most si gnificant bit of the timer mode selection value. 0000 = one-shot mode 0001 = continuous mode 0010 = counter mode 0011 = pwm single output mode 0100 = capture mode 0101 = compare mode 0110 = gated mode 0111 = capture/compare mode 1000 = pwm dual output mode 1001 = capture restart mode 1010 = comparator counter mode
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 87 watchdog timer the watchdog timer (wdt) protects against co rrupt or unreliable software, power faults, and other system-level problems which can place z8 encore! xp ? f0823 series devices into unsuitable operating states. the features of watchdog timer include: ? on-chip rc oscillator ? a selectable time-out response: reset or interrupt ? 24-bit programmable time-out value operation the wdt is a retriggerable one-shot timer that resets or interrupts z8 encore! xp f0823 series devices when the wdt reaches its termin al count. the watchdog timer uses a ded- icated on-chip rc oscillator as its clock source. the watchdog timer operates in only two modes: on and off. once enabled, it always co unts and must be re freshed to prevent a time-out. perform an enab le by executing the wdt instruction or by setting the wdt_ao flash option bit. the wdt_ao bit forces the watchdog ti mer to operate immediately upon reset, even if a wdt instruction has not been executed. the watchdog timer is a 24-bit reloadable down counter that uses three 8-bit registers in the ez8 cpu register space to set the reload value. the nominal wdt time-out period is described by the following equation: where the wdt reload value is the deci mal value of the 24-bit value given by {wdtu[7:0], wdth[7:0], wdtl[7:0]} and th e typical watchdog timer rc oscillator frequency is 10 khz. the watchdog time r cannot be refresh ed after it reaches 000002h . the wdt reload value must no t be set to values below 000004h . table 57 provides information about approxim ate time-out delays for the minimum and maximum wdt reload values. table 57. watchdog timer approximate time-out delays wdt reload value (hex) wdt reload value (decimal) approximate time-out delay (with 10 khz typical wdt oscillator frequency) typical description 000004 4 400 s minimum time-out delay ffffff 16,777,215 28 minutes maximum time-out delay wdt time-out period (ms) wdt reload value 10 ------------------ -------------- ---------- =
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 88 watchdog timer refresh when first enabled, the wdt is loaded with the value in the watchdog timer reload registers. the watchdog timer counts down to 000000h unless a wdt instruction is executed by the ez8 cpu. execution of the wdt instruction causes the down counter to be reloaded with the wdt reload value stored in the watchdog timer reload registers. counting resumes following the reload operation. when z8 encore! xp ? f0823 series devices are operating in debug mode (using the ocd), the watchdog timer is continuously refreshed to prevent any watchdog timer time-outs. watchdog timer time-out response the watchdog timer times ou t when the counter reaches 000000h . a time-out of the watchdog timer generates either an interru pt or a system reset. the wdt_res flash option bit determines the time-out response of the watchdog time r. for information on programming of the wdt_res flash option bit, see flash option bits on page 141. wdt interrupt in normal operation if configured to generate an interrupt when a time-out occu rs, the watchdog timer issues an interrupt request to the interrupt controller and sets the wdt status bit in the watchdog timer control register. if interrupts are enable d, the ez8 cpu respon ds to the interrupt request by fetching the watchdog timer inte rrupt vector and executing code from the vector address. after time-out and interrupt ge neration, the watchdog timer counter rolls over to its maximum value of fffffh and continues counting. the watchdog timer counter is not automatically re turned to its reload value. the reset status register (see reset status register on page 28) must be read before clearing the wdt interrupt. this read clears the wdt time-out flag and prevents further wdt interrupts for im mediately occurring. wdt interrupt in stop mode if configured to generate an interrupt when a time-out occu rs and z8 encore! xp f0823 series are in stop mode, the watchdog timer automatically initiat es a stop mode recov- ery and generates an interrupt reques t. both the wdt status bit and the stop bit in the watchdog timer control register are set to 1 following a wdt time-out in stop mode. for more information on stop mode recovery, see reset and stop mode recovery on page 21. if interrupts are enabled, following completi on of the stop mode recovery the ez8 cpu responds to the interrupt request by fetching the watchdog timer interrupt vector and executing code from the vector address.
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 89 wdt reset in normal operation if configured to generate a reset when a tim e-out occurs, the watchdog timer forces the device into the system reset state. the wd t status bit in the watchdog timer control register is set to 1. for more information on system reset, see reset and stop mode recovery on page 21. wdt reset in stop mode if configured to generate a reset when a time- out occurs and the device is in stop mode, the watchdog timer initiates a stop mode recovery. both the wdt status bit and the stop bit in the watchdog timer control regist er are set to 1 following wdt time-out in stop mode. for more information, see reset and stop mode recovery on page 21. watchdog timer reload unlock sequence writing the unlock sequ ence to the watchdog timer cont rol register (wdtctl) address unlocks the three watchdog timer reload byte registers (wdt u, wdth, and wdtl) to allow changes to the time- out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register. the locking mechanism prevents spurious writes to the reload registers. the fo llowing sequence is required to unlock the watchdog timer reload byte registers (wdtu, wdth, and wdtl) for write access. 1. write 55h to the watchdog timer control register (wdtctl). 2. write aah to the watchdog timer control register (wdtctl). 3. write the watchdog timer reload upper byte register (wdtu). 4. write the watchdog timer reload high byte register (wdth). 5. write the watchdog timer relo ad low byte register (wdtl). all three watchdog timer reload registers must be written in the order just listed. there must be no other register writes between each of these operations. if a register write occurs, the lock state machine resets and no fu rther writes can occur unless the sequence is restarted. the value in the watchdog timer re load registers is loaded into the counter when the watchdog timer is first enabled and every time a wdt instruction is executed. watchdog timer control register definitions watchdog timer control register the watchdog timer control (wdtctl) register is a write-only control register. writing the 55h , aah unlock sequence to the wdtctl register address unlocks the three
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 90 watchdog timer reload byte registers (wdt u, wdth, and wdtl) to allow changes to the time-out period. these write operations to the wdtctl register address produce no effect on the bits in the wdtctl register . the locking mechanis m prevents spurious writes to the reload registers. this register address is shared with the read-only reset status register. wdtunlk?watchdog timer unlock the software must write the correct unlocking se quence to this register before it is allowed to modify the contents of the watchdog timer reload registers. watchdog timer reload upper, high and low byte registers the watchdog timer reload upper, hi gh and low byte (wdtu, wdth, wdtl) registers ( tables 59 through table 61 ) form the 24-bit reload valu e that is loaded into the watchdog timer when a wdt instruction executes. the 24-bit reload value is {wdtu[7:0], wdth[7:0], wdtl[7:0]}. writing to these registers sets the appropriate reload value. reading from these registers returns the current watchdog timer count value. the 24-bit wdt reload value must not be set to a value less than 000004h . table 58. watchdog timer control register (wdtctl) bits 7 6 5 4 3 2 1 0 field wdtunlk reset xxxxxxxx r/w wwwwwwww addr ff0h caution:
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 91 wdtu?wdt reload upper byte most significant byte (msb), bits[23: 16], of the 24-bit wdt reload value. wdth?wdt reload high byte middle byte, bits[15:8], of the 24-bit wdt reload value. wdtl?wdt reload low least significant byte (lsb), bits[7 :0], of the 24-bit wdt reload value. table 59. watchdog timer reload upper byte register (wdtu) bits 7 6 5 4 3 2 1 0 field wdtu reset 00h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff1h r/w*?read returns the current wdt count value. write sets the appropriate reload value. table 60. watchdog timer reload high byte register (wdth) bits 7 6 5 4 3 2 1 0 field wdth reset 04h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff2h r/w*?read returns the current wdt count value. write sets the appropriate reload value. table 61. watchdog timer reload low byte register (wdtl) bits 7 6 5 4 3 2 1 0 field wdtl reset 00h r/w r/w* r/w* r/w* r/w* r/w* r/w* r/w* r/w* addr ff3h r/w*?read returns the current wdt count value. write sets the appropriate reload value.
ps024314-0308 watchdog timer z8 encore! xp ? f0823 series product specification 92
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 93 universal asynchronous receiver/transmitter the universal asynchronous re ceiver/transmitter (uart) is a full-duplex communication channel capable of handling asynchronous data transfers. the uart uses a single 8-bit data mode with selectable parity. the features of uart include: ? 8-bit asynchronous data transfer ? selectable even- and odd-parity generation and checking ? option of one or two stop bits ? separate transmit and receive interrupts ? framing, parity, overrun, and break detection ? separate transmit and receive enables ? 16-bit baud rate generator (brg) ? selectable multiprocessor (9-bit) mode wi th three configurable interrupt schemes ? brg can be configured and used as a basic 16-bit timer ? driver enable output for external bus transceivers architecture the uart consists of three primary functional blocks: transmitter, rece iver, and baud rate generator. the uart?s transmitter and receiv er function independently, but employ the same baud rate and data format. figure 10 displays the uart architecture.
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 94 figure 10. uart block diagram operation data format the uart always transmits and receives data in an 8-bit data format, least-significant bit (lsb) first. an even or odd par ity bit can be added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 11 and figure 12 display the asynchronous data form at employed by the uart without par- ity and with parity, respectively. receive shifter receive data transmit data transmit shift txd rxd system bus parity checker parity generator receiver control control registers transmitter control cts status register register register register baud rate generator de with address compare
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 95 figure 11. uart asynchronous data format without parity figure 12. uart asynchronous data format with parity transmitting data using the polled method follow the steps below to transmit data using the polled method of operation: 1. write to the uart baud rate high and low byte registers to set the required baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register, if multiprocessor mode is appropriate, to enable multiprocessor (9-bit) mode functions. 4. set the multiprocessor mode select ( mpen ) bit to enable mu ltiprocessor mode. 5. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission ? set the parity enable bit ( pen ), if parity is approp riate and multiprocessor mode is not enabled, and select either even or odd parity ( psel ). ? set or clear the ctse bit to enable or disable control from the remote receiver using the cts pin. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 data field lsb msb idle state of line stop bit(s) 1 2 1 0 start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 96 6. check the tdre bit in the uart status 0 register to determine if the transmit data register is empty (indicated by a 1). if empty, continue to step 7 . if the transmit data register is full (indicated by a 0), contin ue to monitor the tdre bit until the transmit data register becomes available to receive new data. 7. write the uart control 1 register to select the outgoing address bit. 8. set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 9. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 10. make any changes to the multiprocessor bit transmitter ( mpbt ) value, if appropriate and multiprocessor mode is enabled,. 11. to transmit additional bytes, return to step 5 . transmitting data using th e interrupt-driven method the uart transmitter interrupt indicates the av ailability of the transmit data register to accept new data for transmission. follow th e steps below to configure the uart for interrupt-driven data transmission: 1. write to the uart baud rate high and low byte registers to set the appropriate baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the acceptable priority. 5. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if multiprocessor mode is appropriate. 6. set the multiprocessor mode select ( mpen ) to enable multiprocessor mode. 7. write to the uart control 0 register to: ? set the transmit enable bit ( ten ) to enable the uart for data transmission. ? enable parity, if appropriate and if mu ltiprocessor mode is not enabled, and select either even or odd parity. ? set or clear ctse to enable or disable control fro m the remote receiver using the cts pin. 8. execute an ei instruction to enable interrupts.
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 97 the uart is now configured for interrupt-d riven data transmission. because the uart transmit data register is empty, an interr upt is generated immediately. when the uart transmit interrupt is detected, the associated interrupt service routine (isr) performs the following: 1. write the uart control 1 register to selec t the multiprocessor bit for the byte to be transmitted: set the multiprocessor bit transmitter ( mpbt ) if sending an address byte, clear it if sending a data byte. 2. write the data byte to the uart transmit data register. the transmitter automatically transfers the data to the transmit sh ift register and transmits the data. 3. clear the uart transmit interrupt bit in th e applicable interrupt request register. 4. execute the iret instruction to return from the interrupt-service routine and wait for the transmit data register to again become empty. receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the uart baud rate high and low byte registers to set an acceptable baud rate for the incoming data stream. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. write to the uart control 1 register to enable multiproc essor mode functions, if appropriate. 4. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity 5. check the rda bit in the uart status 0 re gister to determine if the receive data register contains a valid data byte (indicated by a 1). if rda is set to 1 to indicate available data, continue to step 6 . if the receive data register is empty (indicated by a 0), continue to monitor the rda bit awaiting reception of the valid data. 6. read data from the uart receive data register. if operati ng in multiprocessor (9-bit) mode, further actions may be re quired depending on the multiprocessor mode bits mpmd[1:0]. 7. return to step 4 to receive additional data.
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 98 receiving data using the interrupt-driven method the uart receiver interrupt indicates the availability of new data (as well as error conditions). follow the steps below to config ure the uart receiver for interrupt-driven operation: 1. write to the uart baud rate high and low byte registers to set the acceptable baud rate. 2. enable the uart pin functions by config uring the associated gpio port pins for alternate function operation. 3. execute a di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart receiver interrupt and set the acceptable priority. 5. clear the uart receiver interrupt in th e applicable interrupt request register. 6. write to the uart control 1 register to enable multiprocessor (9-bit) mode functions, if appropriate. ? set the multiprocessor mode select ( mpen ) to enable multiprocessor mode ? set the multiprocessor mode bits, mpmd[1:0] , to select the acceptable address matching scheme ? configure the uart to interrupt on received data and errors or errors only (interrupt on errors only is unlikely to be useful for z8 encore! xp devices without a dma block) 7. write the device address to the address compare register (automatic multiprocessor modes only). 8. write to the uart control 0 register to: ? set the receive enable bit ( ren ) to enable the uart for data reception ? enable parity, if appropriate and if multip rocessor mode is not enabled, and select either even or odd parity 9. execute an ei instruction to enable interrupts. the uart is now configured for interrupt-driven data reception. when the uart receiver interrupt is detected, the associat ed interrupt service rou tine (isr) performs the following: 1. checks the uart status 0 register to dete rmine the source of the interrupt - error, break, or received data. 2. reads the data from the uart receive data register if the interrupt was because of data available. if operating in multiproc essor (9-bit) mode, further actions may be required depending on the mult iprocessor mode bits mpmd[1:0].
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 99 3. clears the uart receiver interrupt in th e applicable interrupt request register. 4. executes the iret instruction to return from the in terrupt-service routine and await more data. clear to send (cts ) operation the cts pin, if enabled by the ctse bit of the uart control 0 register, performs flow control on the outgoing transmit datastream. the clear to send (cts ) input pin is sampled one system clock before beginning any new character transmission. to delay transmission of the next data character, an external receiver must deassert cts at least one system clock cycle before a new data transm ission begins. for multiple character trans- missions, this action is typically perform ed during stop bit transmission. if cts deasserts in the middle of a character transmission, the current character is sent completely. multiprocessor (9-bit) mode the uart has a multiprocessor (9-bit) mode that uses an extra (9 th ) bit for selective communication when a number of processors share a common uart bus. in multiprocessor mode (also referred to as 9-bit mode), the multiprocessor bit ( mp ) is transmitted immediately following the 8-bits of data and immediately preceding the stop bit(s) as displayed in figure 13 . the character format is given below: figure 13. uart asynchronous multiprocessor mode data format in multiprocessor (9-bit) mode , the parity bit location (9 th bit) becomes the multiprocessor control bit. the uart control 1 and st atus 1 registers provide multiprocessor (9-bit) mode control and st atus information. if an automatic address matching scheme is enable d, the uart address compare register holds the network address of the device. multiprocessor (9-bit) mode receive interrupts when multiprocessor mode is enabled, the uart only processes frames addressed to it. the determination of whether a frame of data is addressed to the uart can be made start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 mp data field lsb msb idle state of line stop bit(s) 1 2 1 0
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 100 in hardware, software or so me combination of the two, depending on the multiprocessor configuration bits. in general, the address co mpare feature reduces the load on the cpu, because it does not require access to the uart when it receives data directed to other devices on the multi-node network. the fo llowing three multip rocessor modes are available in hardware: ? interrupt on all address bytes ? interrupt on matched address byte s and correctly framed data bytes ? interrupt only on correctly framed data bytes these modes are selected with mpmd[1:0] in the uart control 1 register. for all multiprocessor modes, bit mpen of the uart control 1 register must be set to 1. the first scheme is enabled by writing 01b to mpmd[1:0]. in this mode, all incoming address bytes cause an interrupt, while data bytes never cause an interrupt. the interrupt service routine must manually check the addre ss byte that caused triggered the interrupt. if it matches the uart address, the software clears mpmd[0]. each new incoming byte interrupts the cpu. the software is responsib le for determining the end of the frame. it checks for the end-o f-frame by reading the mprx bit of the uart status 1 register for each incoming byte. if mprx =1, a new frame has begun. if the address of this new frame is different from the uart?s address, mpmd[0] must be set to 1 causing the uart interrupts to go inactive until th e next address byte. if the ne w frame?s address matches the uart?s, the data in the new frame is processed as well. the second scheme requires th e following: set mpmd[1:0] to 10b and write the uart?s address into the uart address compare register. this mo de introduces additional hardware control, inte rrupting only on frames that match the uart?s address. when an incoming address byte does no t match the uart?s address, it is ignored. all successive data bytes in this frame are also ignored. wh en a matching address byte occurs, an inter- rupt is issued and further inte rrupts now occur on each successi ve data byte. when the first data byte in the frame is read, the newfrm bit of the uart status 1 register is asserted. all successive data bytes have newfrm =0. when the next address byte occurs, the hard- ware compares it to the uart?s address. if th ere is a match, the interrupts continues and the newfrm bit is set for the first byte of the new frame. if there is no match, the uart ignores all incoming bytes un til the next address match. the third scheme is enable d by setting mpmd[1:0] to 11b and by writing the uart?s address into the uart address co mpare register. this mode is identical to the second scheme, except that there are no interrupts on address bytes. the first data byte of each frame remains accompanied by a newfrm assertion.
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 101 external driver enable the uart provides a driver enable (de) signal for off-chip bus transceivers. this feature reduces the software overhead associat ed with using a gpio pin to control the transceiver when communicating on a mu lti-transceiver bus, such as rs-485. driver enable is an active high signal that envelopes the entire transmitted data frame including parity and stop bits as displayed in figure 14 . the driver enable signal asserts when a byte is written to the uart transmit data register. the driver enable signal asserts at least one uart bit period and no greater than two uart bit periods before the start bit is transmitted. this allows a setup time to enable the transceiver. the driver enable signal deasserts one system clock period after the final stop bit is transmitted. this one system clock delay allows both time for da ta to clear the transc eiver before disabling it, as well as the ability to dete rmine if another character follo ws the current character. in the event of back to back characters (new data must be written to the transmit data register before the previous character is co mpletely transmitted) the de signal is not deasserted between characters. the depol bit in the uart control register 1 sets the polarity of the driver enable signal. figure 14. uart driver enable signal timing (shown with 1 stop bit and parity) the driver enable to start bit setup time is calculated as follows: uart interrupts the uart features separate interrupts for the transmitter and the rece iver. in addition, when the uart primary functionality is disab led, the baud rate generator can also function as a basic timer with interrupt capability. start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity data field lsb msb idle state of line stop bit 1 1 0 0 1 de 1 baud rate (hz) ---------------------------------------- - ?? ?? de to start bit setup time (s) 2 baud rate (hz) ---------------------------------------- - ?? ?? ?
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 102 transmitter interrupts the transmitter generates a single interrupt when the transmit data register empty bit ( tdre ) is set to 1. this indicates that the tr ansmitter is ready to accept new data for transmission. the tdre interrupt occurs after the transmit shift register has shifted the first bit of data out. the transmit data regist er can now be written with the next character to send. this action provides 7 bit periods of latency to load the tr ansmit data register before the transmit shift register completes shifting the current character. writing to the uart transmit data register clears the tdre bit to 0. receiver interrupts the receiver generates an interrupt when any of the following occurs: ? a data byte is received and is available in the uart receive data register. this interrupt can be disabled independently of the other rece iver interrupt sources. the received data in- terrupt occurs after the receive character has been received and placed in the receive data register. to avoid an overrun error, software must respond to this re ceived data available condition before the next charac ter is completely received. in multiprocessor mode ( mpen = 1), the receive data interrupts are dependent on the multiprocessor configuration a nd the most recent address byte. ? a break is received ? an overrun is detected ? a data framing error is detected uart overrun errors when an overrun error conditio n occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been read, the uart st atus 0 register is updated to indicate the overrun condition (and break detect, if applicable). the rda bit is set to 1 to indicate that the receive data register contains a data byte. however, because the overrun error occurred, this byte cannot contain valid data and must be ignored. the brkd bit indicates if the overrun was caused by a break condition on the line. after reading the status byte indicating an overrun erro r, the receive data register must be read again to clear the error bits is the uart status 0 register. updates to the receive data register occur only when the next data word is received. uart data and error handling procedure figure 15 displays the recommended procedure for use in uart receiver interrupt service routines. note:
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 103 figure 15. uart receiver in terrupt service routine flow baud rate generator interrupts if the baud rate generator (brg) interrupt en able is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this conditio n allows the baud rate generator to function as an additiona l counter if the uart functionality is not employed. uart baud rate generator the uart baud rate generator creates a lo wer frequency baud rate clock for data transmission. the input to the baud rate ge nerator is the system clock. the uart baud rate high and low byte registers combine to create a 16-bit baud rate divisor value receiver errors? no yes read status discard data read data which interrupt receiver ready clears rda bit and resets error bits read data
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 104 (brg[15:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calculated usin g the following equation: when the uart is disabled, the baud rate generator functions as a basic 16-bit timer with interrupt on time-out. follow the steps below to configure the baud rate generator as a timer with interrupt on time-out: 1. disable the uart by clearing the ren and te n bits in the uart control 0 register to 0. 2. load the acceptable 16-bit count value into the uart ba ud rate high and low byte registers. 3. enable the baud rate generator timer fu nction and associated interrupt by setting the birq bit in the uart control 1 register to 1. when configured as a general purpose timer, th e interrupt interval is calculated using the following equation: uart control register definitions the uart control registers support the uart and the associated infrared encoder/ decoders. for more in formation on the infrared operation, see infrared encoder/decoder on page 113. uart transmit data register data bytes written to the uar t transmit data register ( table 62 ) are shifted out on the txdx pin. the write-only uart transmit data register shares a register file address with the read-only uart receive data register. txd?transmit data uart transmitter data byte to be shifted out through the txd x pin. table 62. uart transmit data register (u0txd) bits 7 6 5 4 3 2 1 0 field txd reset xxxxxxxx r/w wwwwwwww addr f40h uart data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value -------------------- --------------------- --------------------- ------------------ - = interrupt interval (s) syste m clock period (s) brg[15:0] =
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 105 uart receive data register data bytes received through the rxd x pin are stored in the uart receive data register ( table 63 ). the read-only uart receive data register shares a register file address with the write-only uart transmit data register. rxd?receive data uart receiver data byte from the rxd x pin uart status 0 register the uart status 0 and status 1 registers ( table 64 and table 65 ) identify the current uart operating configuration and status. rda?receive data available this bit indicates that the uart receive data register has received data. reading the uart receive data register clears this bit. 0 = the uart receive data register is empty 1 = there is a byte in the uart receive data register pe?parity error this bit indicates that a parity error h as occurred. reading the uart receive data register clears this bit. 0 = no parity e rror has occurred 1 = a parity error has occurred oe?overrun error this bit indicates that an overrun error has o ccurred. an overrun occurs when new data is table 63. uart receive data register (u0rxd) bits 7 6 5 4 3 2 1 0 field rxd reset xxxxxxxx r/w rrrrrrrr addr f40h table 64. uart status 0 register (u0stat0) bits 7 6 5 4 3 2 1 0 field rda pe oe fe brkd tdre txe cts reset 000001 1 x r/w rrrrrr r r addr f41h
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 106 received and the uart receive data register has not been read. if the rda bit is reset to 0, reading the uart receive da ta register clears this bit. 0 = no overrun error occurred 1 = an overrun error occurred fe?framing error this bit indicates that a framing error (no st op bit following data reception) was detected. reading the uart receive data register clears this bit. 0 = no framing error occurred 1 = a framing error occurred brkd?break detect this bit indicates that a break occurred. if the data bits, parity/multip rocessor bit, and stop bit(s) are all 0s this bit is set to 1. readin g the uart receive data register clears this bit. 0 = no break occurred 1 = a break occurred tdre?transmitter data register empty this bit indicates that the uart transmit data register is empty and ready for additional data. writing to the uart transmit data register resets this bit. 0 = do not write to the uart transmit data register 1 = the uart transmit data register is ready to receive an additional byte to be transmit- ted txe?transmitter empty this bit indicates that the transmit shift regist er is empty and character transmission is fin- ished. 0 = data is currently transmitting 1 = transmission is complete cts?cts signal when this bit is read it re turns the level of the cts signal. this signal is active low. uart status 1 register this register contains multipro cessor control and status bits. table 65. uart status 1 register (u0stat1) bits 7 6 5 4 3 2 1 0 field reserved newfrm mprx reset 000000 0 0 r/w rrrrr/wr/wr r addr f44h
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 107 reserved?r/w bits must be 0 during writes; 0 when read. newfrm?status bit denoting the start of a new frame. reading the uart receive data register resets this bit to 0. 0 = the current byte is not the first data byte of a new frame 1 = the current byte is the fi rst data byte of a new frame mprx?multiprocessor receive returns the value of the most recent multip rocessor bit received. reading from the uart receive data register resets this bit to 0. uart control 0 and co ntrol 1 registers the uart control 0 and control 1 registers ( table 66 and table 67 ) configure the properties of the uart?s transmit and recei ve operations. the uar t control registers must not be written while the uart is enabled. ten?transmit enable this bit enables or di sables the transmitter. the enable is also controlled by the cts signal and the ctse bit. if the cts signal is low and the ctse bit is 1, the transmitter is enabled. 0 = transmitter disabled 1 = transmitter enabled ren?receive enable this bit enables or disables the receiver. 0 = receiver disabled 1 = receiver enabled ctse?cts enable 0 = the cts signal has no effect on the transmitter 1 = the uart recognizes the cts signal as an enable control from the transmitter pen?parity enable this bit enables or disables parity. even or odd is determined by the psel bit. 0 = parity is disabled 1 = the transmitter sends data with an additio nal parity bit and the receiver receives an additional parity bit table 66. uart control 0 register (u0ctl0) bits 7 6 5 4 3 2 1 0 field ten ren ctse pen psel sbrk stop lben reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f42h
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 108 psel?parity select 0 = even parity is transmitted an d expected on all received data 1 = odd parity is transmitted an d expected on all received data sbrk?send break this bit pauses or breaks data transmission. sending a break interrupts any transmission in progress, so ensure that the transmitter has finished sending da ta before setting this bit. 0 = no break is sent 1 = forces a break condition by setting th e output of the transmitter to zero stop?stop bit select 0 = the transmitter sends one stop bit 1 = the transmitter sends two stop bits lben?loop back enable 0 = normal operation 1 = all transmitted data is looped back to the receiver mpmd[1:0]?multip rocessor mode if multiprocessor (9-b it) mode is enabled, 00 = the uart generates an interrupt requ est on all received bytes (data and address) 01 = the uart generates an interrupt request only on received address bytes 10 = the uart generates an interrupt reques t when a received address byte matches the value stored in the address compare register and on all successive data bytes until an address mismatch occurs 11 = the uart generates an interrupt reques t on all received data bytes for which the most recent address byte matched the value in the address compare register mpen?multiprocessor (9-bit) enable this bit is used to enable multiprocessor (9-bit) mode. 0 = disable multiprocessor (9-bit) mode 1 = enable multipro cessor (9-bit) mode mpbt?multiprocessor bit transmit this bit is applicable only when multiproc essor (9-bit) mode is enabled. the 9th bit is used by the receiving device to determine if the data byte co ntains address or data infor- mation. table 67. uart control 1 register (u0ctl1) bits 7 6 5 4 3 2 1 0 field mpmd[1] mpen mpmd[0] mpbt depol brgctl rdairq iren reset 000000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w addr f43h
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 109 0 = send a 0 in the multipro cessor bit location of the data stream (data byte) 1 = send a 1 in the multipro cessor bit location of the data stream (address byte) depol?driver enable polarity 0 = de signal is active high 1 = de signal is active low brgctl?baud rate control this bit causes an alternate uart behavior de pending on the value of the ren bit in the uart control 0 register. when the uart receiver is not enabled (ren=0), this bit determines whether the baud rate generator issues interrupts. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = the baud rate generator generates a receive interrupt when it counts down to 0. reads from the baud rate high and low byte registers return the current brg count value. when the uart receiver is enabled (ren=1), this bit allows reads from the baud rate registers to return the brg count value instead of the reload value. 0 = reads from the baud rate high and low byte registers return the brg reload value. 1 = reads from the baud rate high and low by te registers return the current brg count value. unlike the timers, there is no mechan ism to latch the low byte when the high byte is read. rdairq ?receive data interrupt enable 0 = received data and receiver errors genera tes an interrupt request to the interrupt controller. 1 = received data does not generate an interrupt request to the interrupt controller. only receiver errors generate an interrupt request. iren?infrared encoder/decoder enable 0 = infrared encoder/decoder is di sabled. uart operates normally. 1 = infrared encoder/decoder is enabled. the uart transmits and r eceives data through the infrared en coder/decoder. uart address compare register the uart address compare register stores th e multi-node network address of the uart. when the mpmd[1] bit of uart control register 0 is set, all incoming address bytes are compared to the value stored in the address compare regi ster. receive interrupts and rda assertions only occur in the event of a match.
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 110 comp_addr?compare address this 8-bit value is compared to incoming address bytes. uart baud rate high and low byte registers the uart baud rate high and low byte registers ( table 69 and table 70 ) combine to create a 16-bit baud rate divisor value (brg[1 5:0]) that sets the data transmission rate (baud rate) of the uart. the uart data rate is calcula ted using the following equation: for a given uart data rate, calculate the in teger baud rate divisor value using the following equation: table 68. uart address compare register (u0addr) bits 7 6 5 4 3 2 1 0 field comp_addr reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f45h table 69. uart baud rate high byte register (u0brh) bits 7 6 5 4 3 2 1 0 field brh reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f46h table 70. uart baud rate low byte register (u0brl) bits 7 6 5 4 3 2 1 0 field brl reset 11111111 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f47h uart baud rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- ---------------------- --------------------- ------------------ - = uart baud rate divisor value (brg) round system clock frequency (hz) 16 uart data rate (bits/s) --------------- ----------------- ------------------ --------------- - ?? ?? =
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 111 the baud rate error relative to the acceptable baud rate is calculated usin g the following equation: for reliable communication, the uart baud rate error must never exceed five percent. table 71 provides information abou t data rate errors for 5.5296 mhz system clock. table 71. uart baud rates 5.5296 mhz system clock acceptable rate (khz) brg divisor (decimal) actual rate (khz) error (%) 1250.0 n/a n/a n/a 625.0 n/a n/a n/a 250.0 1 345.6 38.24 115.2 3 115.2 0.00 57.6 6 57.6 0.00 38.4 9 38.4 0.00 19.2 18 19.2 0.00 9.60 36 9.60 0.00 4.80 72 4.80 0.00 2.40 144 2.40 0.00 1.20 288 1.20 0.00 0.60 576 0.60 0.00 0.30 1152 0.30 0.00 uart baud rate error (%) 100 actual data rate desired data rate ? desired data rate --------------- ------------------ ------------------ ----------------- ---------------- - ?? ?? =
ps024314-0308 universal asynchronous receiver/transmitter z8 encore! xp ? f0823 series product specification 112
ps024314-0308 infrared encoder/decoder z8 encore! xp ? f0823 series product specification 113 infrared encoder/decoder z8 encore! xp ? f0823 series products contain a fully-functional, high-performance uart with infrared encoder/decoder (endec). th e infrared endec is integrated with an on-chip uart to allow easy communication between the z8 encore ! xp and irda phys- ical layer specification, version 1.3-comp liant infrared transcei vers. infrared communi- cation provides secure, reliable, low-cost, po int-to-point communication between pcs, pdas, cell phones, printers and other infrared enabled devices. architecture figure 16 displays the architecture of the infrared endec. figure 16. infrared data communication system block diagram operation when the infrared endec is en abled, the transmit data from the associated on-chip uart is encoded as digital signals in accordance with the irda standard and output to the infrared transceiver through th e txd pin. similarly, data received from the infrared transceiver is passed to the infrared endec th rough the rxd pin, decoded by the infrared interrupt signal rxd txd infrared encoder/decoder uart rxd txd system clock i/o address data infrared transceiver rxd txd baud rate clock (endec)
ps024314-0308 infrared encoder/decoder z8 encore! xp ? f0823 series product specification 114 endec, and passed to the uart. commun ication is half-duplex, which means simultaneous data transmission and reception is not allowed. the baud rate is set by the uart?s baud rate generator and supports irda standard baud rates from 9600 baud to 115.2 kbaud. higher baud rates are possible, but do not meet irda specifications. the uart must be enabled to use the infrared endec. the infrared endec data rate is calculated us ing the following equation: transmitting irda data the data to be transmitted using the infrared transceiver is first se nt to the uart. the uart?s transmit signal (txd) and baud rate clock are used by the irda to generate the modulation signal (ir_txd) that drives th e infrared transceiver. each uart/infrared data bit is 16 clocks wide. if the data to be transmitted is 1, the ir_txd signal remains low for the full 16 clock period. if the data to be transmitted is 0, the transmitter first outputs a 7 clock low period, followed by a 3 clock high pulse. finally, a 6 clock low pulse is output to complete the full 16 clock data period. figure 17 displays irda data transmis- sion. when the infrared endec is enabled, the uart?s txd signal is internal to z8 encore! xp ? f0823 series products while the ir_txd signal is output through the txd pin. figure 17. infrared data transmission infrared data rate (bits/s) system clock frequency (hz) 16 uart baud rate divisor value ------------------- --------------------- --------------------- ------------------- - = baud rate ir_txd uart?s 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 7-clock delay 3 clock pulse txd clock
ps024314-0308 infrared encoder/decoder z8 encore! xp ? f0823 series product specification 115 receiving irda data data received from the infrare d transceiver using the ir_rxd signal through the rxd pin is decoded by the infrared endec and passed to the uart. the uart?s baud rate clock is used by the infrared endec to generate th e demodulated signal (rxd) that drives the uart. each uart/infrared da ta bit is 16-clocks wide. figure 18 displays data reception. when the infrared endec is enable d, the uart?s rxd signal is internal to the z8 encore! xp ? f0823 series products while the ir_rxd signal is received through the rxd pin. figure 18. irda data reception infrared data reception the system clock frequency must be at least 1.0 mhz to ensure proper reception of the 1.4 s minimum width pulses allowed by the irda standard. endec receiver synchronization the irda receiver uses a local baud rate clock co unter (0 to 15 clock periods) to generate an input stream for the uart and to create a sampling window for detection of incoming pulses. the generated uart input (uart rxd) is delayed by 8 baud rate clock periods with respect to the incoming irda data stream. when a fa lling edge in the input data stream is detected, the endec counter is rese t. when the count reac hes a value of 8, the uart rxd value is updated to reflect the va lue of the decoded data. when the count reaches 12 baud clock periods, the sampling window for the next incoming pulse opens. the window remains open until th e count again reaches 8 (that is, 24 baud clock periods since the previous pulse was detected), giving the endec a sampling window of minus four baud rate uart?s ir_rxd 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 8 clock delay clock rxd 16 clock period 16 clock period 16 clock period 16 clock period start bit = 0 data bit 0 = 1 data bit 1 = 0 data bit 2 = 1 data bit 3 = 1 min. 1.4 s pulse caution:
ps024314-0308 infrared encoder/decoder z8 encore! xp ? f0823 series product specification 116 baud rate clocks to plus eight baud rate clocks around the expected time of an incoming pulse. if an incoming pulse is detected inside this window th is process is repeated. if the incoming data is a logical 1 (no pulse), the endec returns to the in itial state and waits for the next falling edge. as each falling edge is detected, the endec clock counter is reset, resynchronizing the endec to th e incoming signal, allowing th e endec to tolerate jitter and baud rate errors in the incoming datastream . resynchronizing the endec does not alter the operation of the uart, which ultimately re ceives the data. the uart is only synchro- nized to the incoming data str eam when a start bit is received. infrared encoder/decoder c ontrol register definitions all infrared endec configuration and status information is set by the uart control registers as defined in universal asynchronous receiver/transmitter on page 93. to prevent spurious signals during irda dat a transmission, set the iren bit in the uart control 1 register to 1 to enable the infrared encoder/deco der before enabling the gpio port alternate functio n for the corresponding pin. caution:
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 117 analog-to-digital converter the analog-to-digital converter (adc) converts an analog input signal to its digital representation. the features of this sigma-delta adc include: ? 10-bit resolution ? eight single-ended analog input sources ar e multiplexed with general-purpose i/o ports ? interrupt upon conversion complete ? bandgap generated internal voltage refere nce generator with two selectable levels ? factory offset and gain calibration architecture figure 19 displays the major functional blocks of the adc. an analog multiplexer network selects the adc input from the av ailable analog pins, ana0 through ana7.
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 118 figure 19. analog-to-digital converter block diagram operation data format the output of the adc is an 11-bit, signed, two?s complement digital value. the output generally ranges from 0 to +1023, but offs et errors can cause small negative values. the adc registers return 13 bits of data, bu t the two lsbs are inte nded for compensation use only. when the co mpensation routine is performed on the 13 bit raw adc value, two analog input multiplexer internal voltage reference generator analog input ref input vref adc irq adc data vrefsel 2 11 ana7 ana6 ana5 ana4 ana3 ana2 ana1 ana0 vrefext anain 4
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 119 bits of resolution are lost because of a roundi ng error. as a result, the final value is an 11- bit number. automatic powerdown if the adc is idle (no conversions in progre ss) for 160 consecutive system clock cycles, portions of the adc are automatically powe red down. from this powerdown state, the adc requires 40 system clock cycles to powe rup. the adc powers up when a conversion is requested by the adc control register. single-shot conversion when configured for single-shot conversion, the adc performs a single analog-to-digital conversion on the selected analog input chan nel. after completion of the conversion, the adc shuts down. follow the steps below for setting up the adc and initiating a single- shot conversion: 1. enable the acceptable analog inputs by co nfiguring the general-purpose i/o pins for alternate function. this configuration disa bles the digital input and output drivers. 2. write the adc control/status register 1 to configure the adc ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disa ble the internal reference. the refselh bit is contained in the adc control/status register 1 . 3. write to the adc control register 0 to configure the adc and begin the conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? clear cont to 0 to select a single-shot conversion. ? if the internal voltage reference mu st be output to a pin, set the refext bit to 1. the internal voltage reference must be enabled in this case. ? write the refsell bit of the pair { refselh , refsell } to select the internal voltage reference level or to disable th e internal reference. the refsell bit is contained in the adc control register 0 . ? set cen to 1 to start the conversion. 4. cen remains 1 while the conversion is in progress. a single-shot conversion requires 5129 system clock cycles to complete. if a single-shot conversion is requested from an adc powered-down state, the adc uses 40 additional clock cycles to power-up before beginning the 5129 cycle conversion.
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 120 5. when the conversion is complete, the adc control logic performs the following operations: ? 11-bit two?s-complement result written to {adcd_h[7:0], adcd_l[7:5]}. ? cen resets to 0 to indicate the conversion is complete. 6. if the adc remains idle for 160 consecutive system clock cycles, it is automatically powered-down. continuous conversion when configured for continuous conversion , the adc continuously performs an analog- to-digital conversion on the sel ected analog input. each new data value over-writes the previous value stored in the adc data register s. an interrupt is generated after each con- version. in continuous mode, adc updates are limited by the input signal bandwidth of the adc and the latency of the adc and its digita l filter. step changes at the input are not detected at the next output from the adc. th e response of the adc (in all modes) is lim- ited by the input signal bandwidth and the latency. follow the steps below for setting up the adc and initiating con tinuous conversion: 1. enable the acceptable analog input by conf iguring the general-purpose i/o pins for alternate function. this action disables the digital input and output driver. 2. write the adc control/status register 1 to configure the adc: ? write the refselh bit of the pair { refselh , refsell } to select the internal voltage reference level or to disable th e internal reference. the refselh bit is contained in the adc control/status register 1 . 3. write to the adc control register 0 to configure the adc fo r continuous conversion. the bit fields in the adc control re gister can be written simultaneously: ? write to the anain[3:0] field to select from the available analog input sources (different input pins available depending on the device). ? set cont to 1 to select continuous conversion. ? if the internal vref must be output to a pin, set the refext bit to 1. the internal voltage reference mu st be enabled in this case. ? write the refsell bit of the pair {refselh, refsell} to select the internal voltage reference level or to disable th e internal reference. the refsell bit is contained in adc control register 0 . ? set cen to 1 to start the conversions. caution:
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 121 4. when the first conversion in continuous operation is complete (after 5129 system clock cycles, plus the 40 cycles for powe r-up, if necessary), the adc control logic performs the following operations: ? cen resets to 0 to indicate the first conversion is complete. cen remains 0 for all subsequent conversions in continuous operation. ? an interrupt request is sent to the interrupt controller to indicate the conversion is complete. 5. the adc writes a new data result every 256 system clock cycles. for each completed conversion, the adc control logic performs the following operations: ? writes the 11-bit two?s complement result to {adcd_h[7:0], adcd_l[7:5]}. ? an interrupt request to the interrupt controller denoting co nversion complete. 6. to disable continuous conversion, clear the cont bit in the adc control register to 0. interrupts the adc is able to interrupt the cpu whenev er a conversion has been completed and the adc is enabled. when the adc is disabled, an interrupt is not asserted; however, an interrupt pending when the adc is disabled is not cleared. calibration and compensation z8 encore! xp ? f0823 series adc can be factory ca librated for offset error and gain error, with the compensation data stored in flash memory. alternatively, user code can perform its own calibration, storing the values into flash themselves. factory calibration devices that have been factory calibrated co ntain nine bytes of calibration data in the flash option bit space. this data consists of three bytes for each re ference type. for a list of input modes for which ca libration data exists, see zilog calibration data on page 147. there is 1 byte for offset, 2 bytes for gain correction. user calibration if you have precision references available, its own external calibration can be performed, storing the values into flash themselves.
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 122 software compensation procedure the value read from the adc high and low by te registers are uncompensated. the user mode software must apply gain and offset correction to this un compensated value for maximum accuracy. the following form ula yields the compensated value: where gaincal is the gain calibration byte, offcal is the offset calibration byte and adc uncomp is the uncompensated value read fro m the adc. the offcal value is in two?s complement format, as are the compensated and uncompensated adc values. the offset compensation is performed first, fo llowed by the gain compensation. one bit of resolution is lost because of rounding on both the offset and gain computations. as a result the adc registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10 data bits. also note that in the second term, the multiplication must be performed before the division by 2 16 . otherwise, the second term evaluates to zero incorrectly. although the adc can be used without the ga in and offset compen sation, it does exhibit non-unity gain. designing the adc with su b-unity gain reduces noise across the adc range but requires the adc results to be scaled by a factor of 8/7. adc control register definitions the following sections define the adc control registers. adc control register 0 the adc control register selects the an alog input channel and initiates the analog-to-digital conversion. cen?conversion enable 0 = conversion is complete. writing a 0 produc es no effect. the adc automatically clears this bit to 0 when a co nversion is complete. 1 = begin conversion. writing a 1 to this bit st arts a conversion. if a conversion is already in progress, the conversion restarts. this bit remains 1 until the conversion is complete. table 72. adc control register 0 (adcctl0) bits 7 6 5 4 3 2 1 0 field cen refsell refext cont anain[3:0] reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f70h adc comp adc uncomp offcal ? () adc uncomp offcal ? () ? gaincal () 2 16 ? + = note: caution:
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 123 refsell?voltage reference level select low bit; in conjunction with the high bit (refselh) in adc control/status register 1 , this determines the level of the internal voltage reference; the following de tails the effects of {refselh, refsell}; this reference is independent of the comparator reference. 00= internal reference disabled, reference comes from external pin. 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) refext ? external reference select 0 = external reference buffer is disabled; v ref pin is available for gpio functions 1 = the internal adc reference is buffered and connected to the v ref pin cont 0 = single-shot conversion. adc data is output once at completion of the 5129 system clock cycles. 1 = continuous conversion. adc data updated every 256 system clock cycles. anain[3:0]?analog input select these bits select the analog input for conversion . not all port pins in this list are available in all packages for z8 encore! xp ? f0823 series. for information on the port pins avail- able with each package style, see pin description on page 7. do not enable unavailable analog inputs. usage of these bits changes depending on the buffer mode selected in adc control/status register 1 . for the reserved values, all inpu t switches are disabled to avoid leakage or other undesir- able operation. adc samples taken with reserved bit settings are undefined. single-ended: 0000 = ana0 0001 = ana1 0010 = ana2 0011 = ana3 0100 = ana4 0101 = ana5 0110 = ana6 0111 = ana7 1000 = reserved 1001 = reserved 1010 = reserved 1011 = reserved 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved note:
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 124 adc control/status register 1 the second adc control register contains the voltage reference level selection bit. refselh?voltage reference le vel select high bit; in co njunction with the low bit (refsell) in adc control register 0 , this determines the leve l of the internal voltage reference; the following details the effe cts of {refselh, refsell}; this reference is independent of the comparator reference 00= internal reference disabled, reference comes from external pin 01= internal refere nce set to 1.0 v 10= internal reference set to 2.0 v (default) adc data high byte register the adc data high byte register contains the upper eight bits of the adc output. the output is an 11-bit two?s comple ment value. during a single-sh ot conversion, this value is invalid. access to the adc data high byte re gister is read-only. reading the adc data high byte register latches data in the adc low bits register. adcdh?adc data high byte this byte contains the upper eight bits of th e adc output. these bits are not valid during a single-shot conversion. during a continuous conversion, the most recent conversion out- put is held in this register. the se bits are undefined after a reset. table 73. adc control/status register 1 (adcctl1) bits 7 6 5 4 3 2 1 0 field refselh reserved reset 10000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f71h table 74. adc data high byte register (adcd_h) bits 7 6 5 4 3 2 1 0 field adcdh reset xxxxxxxx r/w rrrrrrrr addr f72h
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 125 adc data low bits register the adc data low byte register contains the lower bits of the adc output as well as an overflow status bit. the output is a 11-bit two?s complement value. during a single-shot conversion, this value is invalid. access to th e adc data low byte register is read-only. reading the adc data high byte register la tches data in the adc low bits register. adcdl?adc data low bits these bits are the least significant three bits of the 11-bits of the adc output. these bits are undefined after a reset. reserved?undefined when read ovf?overflow status 0= an overflow did not occur in th e digital filter for the current sample 1= an overflow did occur in the di gital filter for the current sample table 75. adc data low bits register (adcd_l) bits 7 6 5 4 3 2 1 0 field adcdl reserved ovf reset xxxxxxxx r/w rrrrrrrr addr f73h
ps024314-0308 analog-to-digital converter z8 encore! xp ? f0823 series product specification 126
ps024314-0308 comparator z8 encore! xp ? f0823 series product specification 127 comparator z8 encore! xp ? f0823 series devices feature a ge neral purpose comparator that com- pares two analog input signals. a gpio ( cinp ) pin provides the positive comparator input. the negative input ( cinn ) can be taken from either an external gpio pin or an internal reference. the output is available as an interrupt source or can be routed to an external pin using the gpio multiplex. the features of comparator include: ? two inputs which can be connected up using the gpio multiplex (mux) ? one input can be connected to a programmable internal reference ? one input can be connected to the on-chip temperature sensor ? output can be either an interrupt source or an output to an external pin operation one of the comparator inputs can be connecte d to an internal reference which is a user selectable reference that is user pr ogrammable with 200 mv resolution. the comparator can be powered down to save on supply current. for details, see power control register 0 on page 32. because of the propagation delay of the co mparator, it is not recommended to enable the comparator without first disabling int errupts and waiting for the comparator output to settle. doing so can result in spurious interrupts after comparator enabling. the fol- lowing example shows how to sa fely enable the comparator: di ld cmp0 nop nop ; wait for output to settle clr irq0 ; clear any spurious interrupts pending ei comparator control register definitions comparator control register the comparator control register (cmpctl) configures the comparator inputs and sets the value of the internal voltage reference. caution:
ps024314-0308 comparator z8 encore! xp ? f0823 series product specification 128 inpsel?signal select for positive input 0 = gpio pin used as positive comparator input 1 = temperature sensor used as positive comparator input innsel?signal select for negative input 0 = internal reference disabled, gpio pin used as negative comparator input 1 = internal reference enabled as negative comparator input reflvl?internal reference voltage level this reference is independent of the adc voltage reference. 0000 = 0.0 v 0001 = 0.2 v 0010 = 0.4 v 0011 = 0.6 v 0100 = 0.8 v 0101 = 1.0 v (default) 0110 = 1.2 v 0111 = 1.4 v 1000 = 1.6 v 1001 = 1.8 v 1010?1111 = reserved reserved?r/w bits must be 0 during writes; 0 when read table 76. comparator control register (cmp0) bits 7 6 5 4 3 2 1 0 field inpsel innsel reflvl reserved reset 00010100 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f90h note:
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 129 flash memory the products in z8 encore! xp ? f0823 series features either 8 kb (8192), 4 kb (4096), 2 kb (2048) or 1 kb (1024) of non-volatile flash memory with re ad/write/erase capabil- ity. flash memory can be programmed and erase d in-circuit by either user code or through the on-chip debugger. the flash memory array is arranged in pages with 512 bytes per page. the 512-byte page is the minimum flash block size that can be era sed. each page is divided into 8 rows of 64 bytes. for program/data protection, the flash memo ry is also divided into sectors. in the z8 encore! xp f0823 series, these sectors are e ither 1024 bytes (in the 8 kb devices) or 512 bytes in size (all other memory sizes); ea ch sector maps to a page. page and sector sizes are not generally equal. the first two bytes of the flash program memo ry are used as flash option bits. for more information on their operation, see flash option bits on page 141. table 77 describes the flash memory configuration for each device in the z8 encore! xp f0823 series. figure 20 displays the flash memory arrangement. table 77. z8 encore! xp f0823 series flash memory configurations part number flash size kb (bytes) flash pages program memory addresses flash sector size (bytes) z8f08x3 8 (8192) 16 0000h?1fffh 1024 z8f04x3 4 (4096) 8 0000h?0fffh 512 z8f02x3 2 (2048) 4 0000h?07ffh 512 z8f01x3 1 (1024) 2 0000h?03ffh 512
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 130 figure 20. flash memory arrangement flash information area the flash information area is separate fro m program memory and is mapped to the address range fe00h to ffffh . not all these addresses are accessible. factory trim values for the analog peripherals are stored here. factory calibration data for the adc is also stored here.
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 131 operation the flash controller programs and erases fl ash memory. the flash controller provides the proper flash controls and timing for byte programming, page erase, and mass erase of flash memory. the flash controller contains several prot ection mechanisms to prevent accidental programming or erasure. these mechanism op erate on the page, sector and full-memory levels. the flowchart in figure 21 displays basic flash controlle r operation. the following sub- sections provide details about the various operations (lock, unlock, byte programming, page protect, page unprotect, page select page erase, and mass erase) displayed in figure 21 .
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 132 figure 21. flash controller operation flowchart reset page 73h no yes 8ch no yes program/erase enabled 95h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program page erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 133 flash operation timing using the flash frequency registers before performing either a program or erase operation on flash memory, you must first configure the flash frequency high and low byte registers. the flash frequency regis- ters allow programming and erasing of the fl ash with system clock frequencies ranging from 32 khz (32768 hz) through 20 mhz. the flash frequency high and low byte re gisters combine to form a 16-bit value, ffreq , to control timing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz). this value is calculated using the following equation: flash programming and erasure are not supp orted for system clock frequencies below 32 khz (32768 hz) or above 20 mhz. the flash frequency high and low byte registers must be loaded with the correct value to ensure opera tion of z8 encore! xp ? f0823 series devices. flash code protection ag ainst external access the user code contained within the flash memory can be protected against external access with the on-chip deb ugger. programming the frp flash option bit prevents reading of the user code with the on-chip de bugger. for more information, see flash option bits on page 141 and on-chip debugger on page 151. flash code protection against accidental program and erasure z8 encore! xp f0823 series provides several levels of protection against accidental pro- gram and erasure of the flash memory contents . this protection is pr ovided by a combina- tion of the flash option bits, the register lo cking mechanism, the page select redundancy and the sector level protection co ntrol of the flash controller. flash code protection using the flash option bits the frp and fwp flash option bits combine to prov ide three levels of flash program memory protection as listed in table 78 . for more information, see flash option bits on page 141. ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------------- = caution:
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 134 . flash code protection using the flash controller at reset, the flash controller locks to preven t accidental program or erasure of the flash memory. to program or erase the flash memory, first write the page select register with the target page. unlock the flash controlle r by making two consecutive writes to the flash control register with the values 73h and 8ch , sequentially. the page select register must be rewritten with the same page previously stored there. if the two page select writes do not match, the controller reverts to a locked state. if the two writes match, the selected page becomes active. for more details, see figure 21 . after unlocking a specific page, you can enab le either page program or erase. writing the value 95h causes a page erase only if the active page resides in a sector that is not protected. any other value written to the flash control register locks the flash controller. mass erase is not allowed in the user co de but only in thro ugh the debug port. after unlocking a specific page, you can also wr ite to any byte on that page. after a byte is written, the page remains unlock ed, allowing for subsequent writes to other bytes on the same page. further writes to the flash control re gister cause the active page to revert to a locked state. sector based flash protection the final protection mechanism is implemente d on a per-sector basis. the flash memories of z8 encore! xp devices are divided into ma ximum number of 8 sectors. a sector is 1/8 of the total size of the flash memory, unless this value is smaller than the page size, in which case the sector and page sizes are equal. the sector protect register controls the protecti on state of each flash sector. this register is shared with the page select register. it is accessed by writing 73h followed by 5eh to the flash controller. the next write to the flas h control register targets the sector protect register. the sector protect register is initialized to 0 on reset, putting each sector into an unprotected state. when a bit in the sector protect register is written to 1, the corresponding sector can no longer be writte n or erased by the cpu. external flash pro- gramming through the ocd or via the flash controller bypass mode are unaffected. after table 78. flash code protecti on using the flash option bits fwp flash code protection description 0 programming and erasing disabled for all of flash program memory. in user code programming, page erase, and mass erase are all disabled. mass erase is available through the on-chip debugger. 1 programming, page erase, and mass erase are enabled for all of flash program memory.
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 135 a bit of the sector protect register has been set, it cannot be cleared except by powering down the device. byte programming the flash memory is enabled for byte progr amming after unlocking the flash controller and successfully enabling either mass erase or page erase. when the flash controller is unlocked and mass erase is successfully co mpleted, all program memory locations are available for byte programming. in contrast , when the flash controller is unlocked and page erase is successfully enabled, only the lo cations of the selected page are available for byte programming. an erased flash byte contains all 1?s ( ff h ). the programming operation can only be used to change bits fro m 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requires execution of eith er the page erase or mass erase commands. byte programming is accomplished using the on-chip debugger's write memory command or ez8 cpu execution of the ldc or ldci instructions. for a description of the ldc and ldci instructions, refer to ez8 cpu core user manual (um0128) available for download at www.zilog.com . while the flash controller programs the flash memory, the ez8 cpu idles but the system clock and on-chi p peripherals continue to operate. to exit programming mode and lock the flash, write any value to the flash control register, except the mass erase or page erase commands. the byte at each address of the flash memory cannot be programmed (any bits written to 0) more than twice before an erase cy cle occurs. doing so may result in corrupted data at the target byte. page erase the flash memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select register identifies the page to be erased. only a page residing in an unprotected sector can be erased. with the flash controller unlocke d and the active page set, writing the value 95h to the flash control register initiates the page erase operation. while the flash controller executes the page erase operat ion, the ez8 cpu idles but th e system clock and on-chip peripherals continue to operate. the ez8 cpu resumes operation after the page erase operation completes. if the page erase operation is performed using the on-chip debug- ger, poll the flash status register to determin e when the page erase operation is complete. when the page erase is complete, the flash controller returns to its locked state. mass erase the flash memory can also be mass erased us ing the flash controller, but only by using the on-chip debugger. mass erasing the flas h memory sets all bytes to the value ffh . with the flash controller unlocked and the mass erase successfully enabled, writing the caution:
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 136 value 63h to the flash control register initiates the mass erase operation. while the flash controller executes the mass erase operation, the ez8 cpu idles but the system clock and on-chip peripherals continue to operate. using the on-chip debugger, poll the flash status register to determine when the mass erase operation is complete. when the mass erase is complete, the flash contro ller returns to its locked state. flash controller bypass the flash controller can be bypassed and the control signals for the flash memory brought out to the gpio pins. bypassing the flash controller allows faster row program- ming algorithms by controlling the flash programming signals directly. row programing is recommended for gang programming applications and large volume customers who do not require in-circuit initia l programming of the flash memory. page erase operations are also supported wh en the flash controller is bypassed. for more information on bypassing the flash controller, refer to third-party flash pro- gramming support for z8 encore! (an0117) available for download at www.zilog.com . flash controller beh avior in debug mode the following changes in behavior of th e flash controller occur when the flash controller is accessed us ing the on-chip debugger: ? the flash write protect option bit is ignored ? the flash sector protect register is ig nored for programming and erase operations ? programming operations are not limited to the page selected in the page select register ? bits in the flash sector protect re gister can be written to one or zero ? the second write of the page select regist er to unlock the flash controller is not necessary ? the page select register can be writte n when the flash controller is unlocked ? the mass erase command is enabled through the flash control register for security reasons, flash controller allows only a single page to be opened for write/ erase. when writing multiple flas h pages, the flash controlle r must go through the un- lock sequence again to select another page. caution:
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 137 flash control regi ster definitions flash control register the flash controller must be unlocked usin g the flash control (ftctl) register before programming or erasing the fl ash memory. writing the sequence 73h 8ch , sequentially, to the flash control register unlocks the fl ash controller. when the flash controller is unlocked, the flash memory ca n be enabled for mass erase or page erase by writing the appropriate enable command to the fctl. pa ge erase applies only to the active page selected in flash page select register. mass erase is enabled only through the on-chip debugger. writing an invalid va lue or an invalid sequence re turns the flash controller to its locked state. the write-only flash contro l register shares its register file address with the read-only flash status register. fcmd?flash command 73h = first unlock command 8ch = second unlock command 95h = page erase command (must be third co mmand in sequence to initiate page erase) 63h = mass erase command (m ust be third command in se quence to initiate mass erase) 5eh = enable flash sector protect register access flash status register the flash status register indicates the current state of the flash controller. this register can be read at any time. the read-only flas h status register shares its register file address with the write-onl y flash control register. table 79. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww addr ff8h table 80. flash status register (fstat) bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr addr ff8h
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 138 reserved?0 when read fstat?flash controller status 000000 = flash controller locked 000001 = first unlock comm and received (73h written) 000010 = second unlock co mmand received (8ch written) 000011 = flash controller unlocked 000100 = sector protect register selected 001xxx = program operation in progress 010xxx = page erase operation in progress 100xxx = mass erase op eration in progress flash page select register the flash page select (fps) register shares address space with the flash sector protect register. unless the flash controlle r is unlocked and written with 5eh , writes to this address target the flash page select register. the register is used to select one of the ei ght available flash memory pages to be pro- grammed or erased. each flash page contains 512 bytes of flash memory. during a page erase operation, all flash memory having addr esses with the most significant 7-bits given by fps[6:0] are chosen for program/erase operation. info_en?informat ion area enable 0 = information area us not selected 1 = information area is selected. the inform ation area is mapped into the program mem- ory address space at addresses fe00h through ffffh . page?page select this 7-bit field identifies the flash memory page for page erase and page unlocking. program memory address[15:9] = page[6:0]. for the z8f04x3 devices, the upper 4 bits must always be 0. for the z8f02x3 devices, the upper 5 bits must always be 0. for the z8f01x3 devices, the upper 6 bits must always be 0. table 81. flash page select register (fps) bits 7 6 5 4 3 2 1 0 field info_en page reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 139 flash sector protect register the flash sector protect (fprot) register is shared with the flash page select register. when the flash control register is written with 73h followed by 5eh , the next write to this address targets the flash sector protect re gister. in all other cases, it targets the flash page select register. this register selects one of the 8 available fl ash memory sectors to be protected. the reset state of each sector protect bit is an unprotected state. after a sector is protected by setting its corresponding register bit, it cannot be un protected (the register bit cannot be cleared) without powering down the device. sprot7-sprot0?sector protection each bit corresponds to a 512 bytes flash sect or. for the z8f08x3 devices, the upper 3 bits must be zero. for the z8f04x3 devices all b its are used. for the z8f02x3 devices, the upper 4 bits are unused. for the z8f01x3 devices, the upper 6 bits are unused. flash frequency high and low byte registers the flash frequency high (ffreqh) and lo w byte (ffreql) registers combine to form a 16-bit value, ffreq, to control tim ing for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated us ing the following equation: the flash frequency high and low byte registers must be loaded with the correct value to ensure proper operation of the device. al so, flash programming and erasure is not supported for system clock frequenci es below 20 khz or above 20 mhz. table 82. flash sector protect register (fprot) bits 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff9h ffreq[15:0] ffreqh[ 7:0],ffreql[7:0] {} system clock frequency 1000 ------------------------------------------------------------------ == caution:
ps024314-0308 flash memory z8 encore! xp ? f0823 series product specification 140 ffreqh?flash frequency high byte high byte of the 16-bit flash frequency value ffreql?flash frequency low byte low byte of the 16-bit flash frequency value table 83. flash frequency high byte register (ffreqh) bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ffah table 84. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w addr ffbh
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 141 flash option bits programmable flash option bits allow u ser configuration of certain aspects of z8 encore! xp ? f0823 series operation. the feature configuration data is stored in the flash program memory and load ed into holding registers during reset. the features available for control through the flash option bits include: ? watchdog timer time-out response sele ction?interrupt or system reset ? watchdog timer always on (enabled at reset) ? the ability to prevent unwanted read acce ss to user code in program memory ? the ability to prevent accident al programming and erasure of all or a portion of the user code in program memory ? voltage brownout configuration-always en abled or disabled during stop mode to reduce stop mode power consumption ? factory trimming information for th e internal precision oscillator ? factory calibration values for adc ? factory serialization and random ized lot identifier (optional) operation option bit configuration by reset each time the flash option bits are programme d or erased, the device must be reset for the change to take effect. during any reset operation (system reset, power-on reset, or stop mode recovery), the flash option b its are automatically read from the flash program memory and written to option co nfiguration registers. the option configuration registers control operation of the devices within the z8 encore! xp f0823 series. option bit control is established befo re the device exits reset and the ez8 cpu begins code execution. the option configuration registers are not part of the register file and are not accessible for read or write access. option bit types user option bits the user option bits are contained in the first two bytes of program memory. access to these bits has been provided because these lo cations contain application-specific device
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 142 configurations. the information contained here is lost when page 0 of the program memory is erased. trim option bits the trim option bits are contained in the info rmation page of the flash memory. these bits are factory programmed values required to optimize the operation of onboard analog cir- cuitry and cannot be permanen tly altered. program memory may be erased without endan- gering these values. it is possible to alter working values of these bits by accessing the trim bit address and data registers, but thes e working values are lost after a power loss or any other reset event. there are 32 bytes of trim data. to modify on e of these values the user code must first write a value between 00h and 1fh into the trim bit address register. the next write to the trim bit data register changes the work ing value of the target trim data byte. reading the trim data requires the u ser code to write a value between 00h and 1fh into the trim bit address register. the next read from th e trim bit data register returns the work- ing value of the target trim data byte. the trim address range is from informati on address 20-3f only. the remainder of the information page is not accessible through the trim bit address and data registers. calibration option bits the calibration option bits are also contained in the information page. these bits are fac- tory programmed values intende d for use in software correc ting the device?s analog per- formance. to read these values, the user code must employ the ldc instruction to access the information area of the address space as defined in flash information area on page 15 serialization bits as an optional feature, zilog ? is able to provide factory-programmed serialization. for serialized products, the individual devices are programmed with unique serial numbers. these serial numbers are binary values, four bytes in length. the numbers increase in size with each device, but gaps in the serial sequence may exist. these serial numbers are stored in the flash information page (for more details, see read- ing the flash information page on page 143 and serialization data on page 148) and are unaffected by mass erasure of the device?s flash memory. randomized lot identification bits as an optional feature, zilog is able to provide a factory-programmed random lot identifier. with this feature, all devices in a given production lot are programmed with the same random number. this random number is uniquely regenerated for each successive production lot and is not likely to be repeated. note:
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 143 the randomized lot identifier is a 32 byte bi nary value, stored in the flash information page (for more details, see reading the flash information page on page 143 and random- ized lot identifier on page 149) and is unaffected by mass erasure of the device's flash memory. reading the flash information page the following code example shows how to r ead data from the flash information area. ; get value at info address 60 (fe60h) ldx fps, #%80 ; enable access to flash info page ld r0, #%fe ld r1, #%60 ldc r2, @rr0 ; r2 now contains the calibration value flash option bit contro l register definitions trim bit address register the trim bit address (trmadr) register contains the target address for an access to the trim option bits. table 85. trim bit address register (trmadr) bits 7 6 5 4 3 2 1 0 field trmadr - trim bit address (00h to 1fh) reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff6h
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 144 trim bit data register the trim bid data (trmdr) register contains th e read or write data for access to the trim option bits. flash option bit address space the first two bytes of flash program memory at addresses 0000h and 0001h are reserved for the user-programmable flash option bits. flash program memory address 0000h wdt_res?watchdog timer reset 0 = watchdog timer time-out generates an interrupt request. interrupts must be globally enabled for the ez8 cpu to ackno wledge the interrupt request. 1 = watchdog timer time-out causes a system re set. this setting is the default for unpro- grammed (erased) flash. wdt_ao?watchdog timer always on 0 = watchdog timer is automa tically enabled upon applicat ion of system power. watch- dog timer can not be disabled. 1 = watchdog timer is enabled upon execution of the wdt instruction. once enabled, the table 86. trim bit data register (trmdr) bits 7 6 5 4 3 2 1 0 field trmdr - trim bit data reset 00000000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr ff7h table 87. flash option bits at program memory address 0000h bits 7 6 5 4 3 2 1 0 field wdt_res wdt_ao reserved vbo_ao frp reserved fwp reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0000h note: u = unchanged by reset. r/w = read/write.
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 145 watchdog timer can only be disabled by a reset or stop mode recovery. this setting is the default for unprogrammed (erased) flash. reserved?r/w bits must be 1 during writes; 1 when read. vbo_ao?voltage brownout protection always on 0 = voltage brownout protection can be disab led in stop mode to reduce total power consumption. for the block to be disabled, the power control register bit must also be writ- ten (see power control register 0 on page 32). 1 = voltage brownout protection is always enabled including during stop mode. this setting is the default for un programmed (erased) flash. frp?flash read protect 0 = user program code is inaccessible. limite d control features are available through the on-chip debugger. 1 = user program code is accessible. all on-chip debugger commands are enabled. this setting is the default for un programmed (erased) flash. reserved?must be 1 fwp?flash write protect this option bit provides flash program memory protection: 0 = programming and erasure disabled for all of flash program memory. programming, page erase, and mass erase through user code is disabled. mass erase is available using the on-chip debugger. 1 = programming, page erase, and mass erase are enabled for all of flash program memory. flash program memory address 0001h reserved?r/w must be 1 during writes; 1 when read xtldis?state of crystal oscillator at reset table 88. flash options bits at program memory address 0001h bits 7 6 5 4 3 2 1 0 field reserved xtldis reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr program memory 0001h note: u = unchanged by reset. r/w = read/write.
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 146 this bit only enables the crystal oscillator. it s selection as system clock must be done man- ually. 0 = crystal oscillator is enabled during reset, resulting in longer reset timing 1 = crystal oscillator is disabled during reset, resu lting in shorter reset timing programming the xtldis bit to zero on 8-pin versions of this devi ce prevents any fur- ther communication via the debug pin. this is due to the fact that the xin and dbg functions are shared on pin 2 of this package. do not program this bit to zero on 8-pin devices unless no further debugging or flash programming is required. trim bit address space all available trim bit addresses and their functions are listed in table 89 through table 91 . trim bit address 0000h?reserved reserved?altering this register may result in incorrect device operation. trim bit address 0001h?reserved table 89. trim options bits at address 0000h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0020h note: u = unchanged by reset. r/w = read/write. table 90. trim option bits at 0001h bits 7 6 5 4 3 2 1 0 field reserved reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0021h note: u = unchanged by reset. r/w = read/write. note: warning:
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 147 reserved? altering this re gister may result in incorrect device operation. trim bit address 0002h ipo_trim?internal precision oscillator trim byte contains trimming bits for in ternal precision oscillator. trim bit address 0003h?reserved trim bit address 0004h?reserved zilog calibration data adc calibration data adc_cal?analog-to-digital c onverter calibration values contains factory calibrated values for adc gain and offset compensation. each of the ten supported modes has one byte of offset calibration and two bytes of gain calibration. these values are read by the software to compensate adc measurements as detailed in table 91. trim option bits at 0002h (tipo) bits 7 6 5 4 3 2 1 0 field ipo_trim reset u r/w r/w addr information page memory 0022h note: u = unchanged by reset. r/w = read/write. table 92. adc calibration bits bits 7 6 5 4 3 2 1 0 field adc_cal reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 0060h?007dh note: u = unchanged by reset. r/w = read/write.
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 148 software compensation procedure on page 122. the location of each calibration byte is provided in table 93 on page 148. serialization data s_num? serial number byte the serial number is a unique four-byte binary value. table 93. adc calibration data location info page address memory address compensation usage adc mode reference type 60 fe60 offset single-ended unbuffered internal 2.0 v 08 fe08 gain high byte single-ended unbuffered internal 2.0 v 09 fe09 gain low byte single-ended unbuffered internal 2.0 v 63 fe63 offset single-ended unbuffered internal 1.0 v 0a fe0a gain high byte single-ended unbuffered internal 1.0 v 0b fe0b gain low byte single-ended unbuffered internal 1.0 v 66 fe66 offset single-ended unbuffered external 2.0 v 0c fe0c gain high byte single-ended unbuffered external 2.0 v 0d fe0d gain low byte single-ended unbuffered external 2.0 v table 94. serial number at 001c-001f (s_num) bits 7 6 5 4 3 2 1 0 field s_num reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr information page memory 001c-001f note: u = unchanged by reset. r/w = read/write.
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 149 randomized lot identifier rand_lot? randomized lot id the randomized lot id is a 32 byte binary value that changes for each production lot. table 95. serialization data locations info page address memory address usage 1c fe1c serial number byte 3 (most significant) 1d fe1d serial number byte 2 1e fe1e serial number byte 1 1f fe1f serial number byte 0 (least significant) table 96. lot identification number (rand_lot) bits 7 6 5 4 3 2 1 0 field rand_lot reset uuuuuuuu r/w r/wr/wr/wr/wr/wr/wr/wr/w addr interspersed throughout information page memory note: u = unchanged by reset. r/w = read/write. table 97. randomized lot id locations info page address memory address usage 3c fe3c randomized lot id byte 31 (most significant) 3d fe3d randomized lot id byte 30 3e fe3e randomized lot id byte 29 3f fe3f randomized lot id byte 28 58 fe58 randomized lot id byte 27 59 fe59 randomized lot id byte 26 5a fe5a randomized lot id byte 25 5b fe5b randomized lot id byte 24
ps024314-0308 flash option bits z8 encore! xp ? f0823 series product specification 150 5c fe5c randomized lot id byte 23 5d fe5d randomized lot id byte 22 5e fe5e randomized lot id byte 21 5f fe5f randomized lot id byte 20 61 fe61 randomized lot id byte 19 62 fe62 randomized lot id byte 18 64 fe64 randomized lot id byte 17 65 fe65 randomized lot id byte 16 67 fe67 randomized lot id byte 15 68 fe68 randomized lot id byte 14 6a fe6a randomized lot id byte 13 6b fe6b randomized lot id byte 12 6d fe6d randomized lot id byte 11 6e fe6e randomized lot id byte 10 70 fe70 randomized lot id byte 9 71 fe71 randomized lot id byte 8 73 fe73 randomized lot id byte 7 74 fe74 randomized lot id byte 6 76 fe76 randomized lot id byte 5 77 fe77 randomized lot id byte 4 79 fe79 randomized lot id byte 3 7a fe7a randomized lot id byte 2 7c fe7c randomized lot id byte 1 7d fe7d randomized lot id byte 0 (least significant) table 97. randomized lot id locations (continued) info page address memory address usage
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 151 on-chip debugger z8 encore! xp ? f0823 series devices contain an integrated on-chip debugger (ocd) that provides advanced debu gging features that include: ? single pin interface ? reading and writing of the register file ? reading and writing of program and data memory ? setting of breakpoints and watchpoints ? executing ez8 cpu instructions ? debug pin sharing with general-purpose input -output function to maximize the pins available architecture the on-chip debugger consists of four primar y functional blocks: tr ansmitter, receiver, auto-baud detector/generat or, and debug controller. figure 22 displays the architecture of the ocd. figure 22. on-chip debugger block diagram auto-baud system clock transmitter receiver dbg pin debug controller ez8 cpu control detector/generator
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 152 operation the following sections describes the operation of ocd. ocd interface the ocd uses the dbg pin for communicatio n with an external host. this one-pin interface is a bidirectional open-drain inte rface that transmits and receives data. data transmission is half-duplex, in that transm it and receive cannot occur simultaneously. the serial data on the dbg pin is sent using the standard asynchronous data format defined in rs-232. this pin creates an interface from th e z8 encore! xp f0823 series products to the serial port of a host pc using minimal external hardware.two different methods for connecting the dbg pin to an rs-2 32 interface are displayed in figure 23 and figure 24 . the recommended method is the buff ered implementation depicted in figure 24 . the dbg pin has a internal pull-up resistor which is sufficient for some applications (for more details on the pull-up current, see electrical characteristics on page 193). for ocd operation at higher data rates or in noisy systems, an external pull-up resistor is recommended. for operation of the oc d, all power pins (v dd and av dd ) must be supplied with power, and all ground pins (v ss and av ss ) must be properly grounded. the dbg pin is open- drain and may require an external pull-up resistor to ensure proper operation. figure 23. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (1) caution: rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k ? schottky diode
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 153 figure 24. interfacing the on-chip debugger?s dbg pin with an rs-232 interface (2) debug mode the operating characteristics of the devices in debug mode are: ? the ez8 cpu fetch unit stops, idling the ez8 cp u, unless directed by the ocd to execute specific instructions ? the system clock operates unless in stop mode ? all enabled on-chip peripheral s operate unless in stop mode ? automatically exits halt mode ? constantly refreshes the wa tchdog timer, if enabled. entering debug mode the device enters debug mode fo llowing the operations below: ? the device enters debug mode after the ez8 cpu executes a brk (breakpoint) instruc- tion ? if the dbg pin is held low during the most r ecent clock cycle of system reset, the part enters debug mode upon exiting system reset holding the dbg pin low for an additional 5000 (minimum) clock c ycles after reset (making sure to account for any specified freq uency error if using an internal oscillator) prevents a false interpretatio n of an autobaud sequence (see ocd auto-baud detector/ generator on page 154). ? if the pa2/reset pin is held low while a 32-bit ke y sequence is issued to the pa0/dbg pin, the dbg feature is unlocked. after releasing pa2/reset , it is pulled high. at this rs-232 tx rs-232 rx rs-232 transceiver vdd dbg pin 10 k ? open-drain buffer note:
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 154 point, the pa0/dbg pin can be used to autobaud and cause the device to enter debug mode. for more details, see ocd unlock sequence (8-pin devices only) on page 156. exiting debug mode the device exits debug mode following any of these operations: ? clearing the dbgmode bit in the ocd control register to 0 ? power-on reset ? voltage brownout reset ? watchdog timer reset ? asserting the reset pin low to initiate a reset ? driving the dbg pin low while the device is in stop mode initia tes a system reset ocd data format the ocd interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (lea st-significant bit first), and 1 stop bit as displayed in figure 25 . figure 25. ocd data format when responding to a request for data, the ocd may comm ence transmitting immediately after receiving the stop bit of an incoming frame. therefore, when sending the stop bit, the host must not actively drive the dbg pin high for more than 0.5 bit times. it is recom- mended that, if possible, th e host drives the dbg pin using an open-drain output. ocd auto-baud detector/generator to run over a range of baud rates (data b its per second) with various system clock frequencies, the ocd contains an auto-baud de tector/generator. after a reset, the ocd is idle until it receives data. the ocd requires that the first character sent from the host is the character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits), framed between high bits. the auto -baud detector measures this period and sets the ocd baud rate generator accordingly. the auto-baud detector/generator is clocked by the system clock. the minimum baud rate is the system clock frequency divided by 51 2. for optimal operation with asynchronous startd0d1d2d3d4d5d6d7stop note:
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 155 datastreams, the maximum recommended baud ra te is the system clock frequency divided by eight. the maximum possible baud rate fo r asynchronous datastreams is the system clock frequency divided by four, but this theoretical maximum is possible only for low noise designs with clean signals. table 98 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the ocd receives a serial break (nine or more continuous bits low) the auto-baud detector/generator resets. re configure the auto-baud det ector/generator by sending 80h . ocd serial errors the ocd detects any of the followin g error conditions on the dbg pin: ? serial break (a minimum of nine continuous bits low) ? framing error (received stop bit is low) ? transmit collision (ocd and host simultan eous transmission de tected by the ocd) when the ocd detects one of these errors, it aborts any command currently in progress, transmits a four character long serial brea k back to the host, and resets the auto-baud detector/generator. a framing error or transmit collision may be caused by the host sending a serial break to the ocd. because of the open-drain natu re of the interface, returning a serial break break back to the host only extends the length of the serial break if the host releases the serial break early. the host transmits a serial break on the dbg pin when first connec ting to the z8 encore! xp f0823 series devices or when recovering from an error. a serial break from the host resets the auto-baud generator/detector but does not reset the ocd control register. a serial break leaves the device in debug mode if that is the current mode. the ocd is held in reset until the end of the serial brea k when the dbg pin returns high. because of the open-drain nature of the db g pin, the host sends a serial break to the ocd even if the ocd is transmitting a character. table 98. ocd baud-rate limits system clock frequency (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 5.5296 1382.4 691,200 1.08 0.032768 (32 khz) 4.096 2400 0.064
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 156 ocd unlock sequence (8-pin devices only) because of pin-sharing on the 8-pin device, an unlock sequence must be performed to access the dbg pin. if this sequence is not completed during a system reset, then the pa0/ dbg pin functions only as a gpio pin. the following sequence unlocks the dbg pin: 1. hold pa2/reset low. 2. wait 5 ms for the internal reset sequence to complete. 3. send the following bytes serially to the debug pin: dbg 80h (autobaud) dbg ebh dbg 5ah dbg 70h dbg cdh (32-bit unlock key) 4. release pa2/reset . the pa0/dbg pin is now identical in function to that of the dbg pin on the 20- or 28-pin device. to enter debug mode, re-autobaud and write 80h to the ocd control register (see on-chip debugger commands on page 157). breakpoints execution breakpoints ar e generated using the brk instruction (opcode 00h ). when the ez8 cpu decodes a brk instruction, it signals the ocd. if breakpoints are enabled, the ocd enters debug mode and idles the ez8 cpu. if breakpoints are not enabled, the ocd ignores the brk signal and the brk instruction operates as an nop instruction. breakpoints in flash memory the brk instruction is opcode 00h , which corresponds to the fu lly programmed state of a byte in flash memory. to implement a breakpoint, write 00h to the required break address, overwriting the current instruction. to remove a breakpoi nt, the corresponding page of flash memory must be erased an d reprogrammed with the original data. runtime counter the ocd contains a 16-bit runtime counter . it counts system clock cycles between breakpoints. the counter starts counting when the ocd leaves debug mode and stops counting when it enters debug mode again or when it reaches the maximum count of ffffh .
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 157 on-chip debugger commands the host communicates to th e ocd by sending ocd commands using the dbg interface. during normal operation, only a subset of the ocd commands are available. in debug mode, all ocd commands become available unl ess the user code and control registers are protected by programming the flash read protect option bit ( frp ). the flash read protect option bit prevents the code in memo ry from being read out of z8 encore! xp ? f0823 series products. when this option is enabled, several of the ocd commands are disabled. table 99 on page 162 is a summary of the ocd commands. each ocd com- mand is described in further detail in the bulleted list following this table. table 99 on page 162 also indicates those commands that operate when the device is not in debug mode (normal operation) and those commands that are disabled by programming the flash read protect option bit. debug command command byte enabled when not in debug mode? disabled by flash read protect option bit read ocd revision 00h yes ? reserved 01h ? ? read ocd status register 02h yes ? read runtime counter 03h ? ? write ocd control register 04h yes cannot clear dbgmode bit. read ocd control register 05h yes ? write program counter 06h ? disabled. read program counter 07h ? disabled. write register 08h ? only writes of the flash memory control registers are allowed. additionally, only the mass erase command is allowed to be written to the flash control register. read register 09h ? disabled. write program memory 0ah ? disabled. read program memory 0bh ? disabled. write data memory 0ch ? yes. read data memory 0dh ? ? read program memory crc 0eh ? ? reserved 0fh ? ? step instruction 10h ? disabled.
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 158 in the following list of ocd commands, data and commands sent from the host to the ocd are identified by ? dbg command/data ?. data sent from the ocd back to the host is identified by ? dbg data ?. ? read ocd revision (00h) ?the read ocd revision command determines the ver- sion of the ocd. if ocd comma nds are added, removed, or changed, this revision number changes. dbg 00h dbg ocdrev[15:8] (major revision number) dbg ocdrev[7:0] (minor revision number) ? read ocd status register (02h) ?the read ocd status re gister command reads the ocdstat register. dbg 02h dbg ocdstat[7:0] ? read runtime counter (03h) ?the runtime counter counts system clock cycles in between breakpoints. the 16-bit runtime counter counts up from 0000h and stops at the maximum count of ffffh . the runtime counter is overwritten during the write memo- ry, read memory, write register, read regi ster, read memory crc, step instruction, stuff instruction, and execute instruction commands. dbg 03h dbg runtimecounter[15:8] dbg runtimecounter[7:0] ? write ocd control register (04h) ?the write ocd control register command writes the data that follows to the ocdctl re gister. when the flash read protect option bit is enabled, the dbgmode bit ( ocdctl [7]) can only be set to 1, it cannot be cleared to 0 and the only method of returning the device to normal operating m ode is to reset the device. dbg 04h dbg ocdctl[7:0] ? read ocd control register (05h) ?the read ocd control register command reads the value of the ocdctl register. stuff instruction 11h ? disabled. execute instruction 12h ? disabled. reserved 13h?ffh ? ? debug command command byte enabled when not in debug mode? disabled by flash read protect option bit
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 159 dbg 05h dbg ocdctl[7:0] ? write program counter (06h) ?the write program counter command writes the data that follows to the ez8 cpu?s program counte r (pc). if the device is not in debug mode or if the flash read protect option bit is en abled, the program counter (pc) values are discarded. dbg 06h dbg programcounter[15:8] dbg programcounter[7:0] ? read program counter (07h) ?the read program counte r command reads the value in the ez8 cpu?s program counter (pc). if the device is not in debug mode or if the flash read protect option bit is enabled, this command returns ffffh . dbg 07h dbg programcounter[15:8] dbg programcounter[7:0] ? write register (08h) ?the write register command writes data to the register file. data can be written 1?256 bytes at a time (256 bytes can be written by setting size to 0). if the device is not in debug mode, the address and data values are discarded. if the flash read protect option bit is enabled, only writes to the flash control registers are allowed and all other register write data values are discarded. dbg 08h dbg {4?h0,register address[11:8]} dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? read register (09h) ?the read register command read s data from the register file. data can be read 1?256 bytes at a time (256 bytes can be read by setting size to 0). if the device is not in debug mode or if the flash read protect option bit is enabled, this com- mand returns ffh for all the data values. dbg 09h dbg {4?h0,register address[11:8] dbg register address[7:0] dbg size[7:0] dbg 1-256 data bytes ? write program memory (0ah) ?the write program memory command writes data to program memory. this command is equivalent to the ldc and ldci instructions. data can be written 1?65536 bytes at a time (65536 bytes can be written by setting size to 0). the on-chip flash controller must be writte n to and unlocked for the programming oper- ation to occur. if the flash controller is not unlocked, the data is discarded. if the device
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 160 is not in debug mode or if the flash read pr otect option bit is enab led, the data is dis- carded. dbg 0ah dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read program memory (0bh) ?the read program memory command reads data from program memory. this co mmand is equiva lent to the ldc and ldci instructions. data can be read 1?65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode or if the fl ash read protect option bit is enabled, this command returns ffh for the data. dbg 0bh dbg program memory address[15:8] dbg program memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? write data memory (0ch) ?the write data memory co mmand writes data to data memory. this command is equivalent to the lde and ldei instructions. data can be writ- ten 1?65536 bytes at a time (6553 6 bytes can be written by setting size to 0). if the device is not in debug mode or if the flash read pr otect option bit is enabled, the data is dis- carded. dbg 0ch dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes ? read data memory (0dh) ?the read data memory co mmand reads from data mem- ory. this command is equivalent to the lde and ldei instructions. data can be read 1 to 65536 bytes at a time (65536 bytes can be read by setting size to 0). if the device is not in debug mode, this command returns ffh for the data. dbg 0dh dbg data memory address[15:8] dbg data memory address[7:0] dbg size[15:8] dbg size[7:0] dbg 1-65536 data bytes
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 161 ? read program memory crc (0eh) ?the read program memory cyclic redundan- cy check (crc) command computes and returns the crc of program memory using the 16-bit crc-ccitt polynomial. if the device is not in debug mode, this command re- turns ffffh for the crc value. unlike most othe r ocd read commands, there is a delay from issuing of the command until the ocd returns the data. the ocd reads the program memory, calculates the crc value, and return s the result. the delay is a function of the program memory size and is approximately equal to the sy stem clock period multiplied by the number of bytes in the program memory. dbg 0eh dbg crc[15:8] dbg crc[7:0] ? step instruction (10h) ?the step instruction command steps one assembly instruction at the current program counter (pc) location. if the device is not in debug mode or the flash read protect option bit is enab led, the ocd ignores this command. dbg 10h ? stuff instruction (11h) ?the stuff instruction command steps one assembly instruction and allows specification of the first byte of the instruction. the remaining 0-4 bytes of the instruction are read from program memory. th is command is useful for stepping over in- structions where the first byte of the instru ction has been overwritten by a breakpoint. if the device is not in debug mode or the flas h read protect option bit is enabled, the ocd ignores this command. dbg 11h dbg opcode[7:0] ? execute instruction (12h) ?the execute instruction command allows sending an entire instruction to be executed to the ez 8 cpu. this command can also step over break- points. the number of bytes to send for the instruction depends on the opcode. if the device is not in debug mode or the flash read pr otect option bit is enabled, this command reads and discards one byte. dbg 12h dbg 1-5 byte opcode on-chip debugger control register definitions ocd control register the ocd control register controls the state of the ocd. this register is used to enter or exit debug mode and to enable the brk instruction. it also resets z8 encore! xp ? f0823 series device.
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 162 a reset and stop function can be achieved by writing 81h to this register. a reset and go function can be achieved by writing 41h to this register. if the device is in debug mode, a run function can be implemented by writing 40h to this register. . dbgmode?debug mode the device enters debug mode when this b it is 1. when in debug mode, the ez8 cpu stops fetching new instructions. clearing this bit causes the ez8 cpu to restart. this bit is automatically set when a brk instruction is decoded and br eakpoints are enabled. if the flash read protect option bit is enabled, th is bit can only be cleared by resetting the device. it cannot be written to 0. 0 = z8 encore! xp f0823 series device is operating in normal mode 1 = z8 encore! xp f0823 series device is in debug mode brken?breakpoint enable this bit controls the behavior of the brk instruction (opcode 00h ). by default, breakpoints are disabled and the brk instruction behaves similar to an nop instruction. if this bit is 1, when a brk instruction is decoded, the dbgmode bit of the ocdctl register is automati- cally set to 1. 0 = breakpoints are disabled 1 = breakpoints are enabled dbgack?debug acknowledge this bit enables the debug acknowledge feature. if this bit is set to 1, the ocd sends a debug acknowledge character ( ffh ) to the host when a breakpoint occurs. 0 = debug acknowledge is disabled 1 = debug acknowledge is enabled reserved?0 when read rst?reset setting this bit to 1 resets th e z8f04xa family de vice. the device go es through a normal power-on reset sequence with th e exception that the ocd is no t reset. this bit is auto- matically cleared to 0 at the end of reset. 0 = no effect 1 = reset the flash read protect option bit device table 99. ocd control register (ocdctl) bits 7 6 5 4 3 2 1 0 field dbgmode brken dbgack reserved rst reset 00000000 r/w r/wr/wr/wrrrrr/w
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 163 ocd status register the ocd status register reports status inform ation about the current state of the debugger and the system. dbg?debug status 0 = normal mode 1 = debug mode halt?halt mode 0 = not in halt mode 1 = in halt mode frpenb?flash read protect option bit enable 0 = frp bit enabled, that allows disabling of many ocd commands 1 = frp bit has no effect reserved?0 when read table 100. ocd status register (ocdstat) bits 7 6 5 4 3 2 1 0 field dbg halt frpenb reserved reset 00000000 r/w rrrrrrrr
ps024314-0308 on-chip debugger z8 encore! xp ? f0823 series product specification 164
ps024314-0308 oscillator control z8 encore! xp ? f0823 series product specification 165 oscillator control z8 encore! xp ? f0823 series devices uses thre e possible clocking schemes, each user-selectable: ? on-chip precision trimmed rc oscillator ? external clock drive ? on-chip low power watchdog timer oscillator in addition, z8 encore! xp f0823 series devices contain clock failure detection and recovery circuitry, allowing continued operation despite a fa ilure of the primary oscillator. operation this chapter discusses the logic used to se lect the system clock and handle primary oscillator failures. a description of the specif ic operation of each oscillator is outlined elsewhere in this document. system clock selection the oscillator control block selects from the available clocks. table 101 details each clock source and its usage. table 101. oscillator configuration and selection clock source characteristics required setup internal precision rc oscillator ? 32.8 khz or 5.53 mhz ? 4% accura cy when trimmed ? no external components required ? unlock and write oscillator control register (oscctl) to enable and select oscillator at either 5.53 mhz or 32.8 khz external clock drive ? 0 to 20 mhz ? accuracy dependent on external clock source ? write gpio registers to configure pb3 pin for external clock function ? unlock and write oscctl to select external system clock ? apply external clock signal to gpio internal watchdog timer oscillator ? 10 khz nominal ? 40% accuracy; no external components required ? very low power consumption ? enable wdt if not enabled and wait until wdt oscillator is operating. ? unlock and write oscillator control register (oscctl) to enable and select oscillator
ps024314-0308 oscillator control z8 encore! xp ? f0823 series product specification 166 unintentional accesses to the oscillator control register c an actually stop the chip by switching to a non-functioning oscillator. to prevent this condition, the oscillator con- trol block employs a register unlocking/locking scheme. osc control register unlocking/locking to write the oscillator control register, unlo ck it by making two writes to the oscctl register with the values e7h followed by 18h . a third write to the oscctl register changes the value of the actual register and retu rns the register to a locked state. any other sequence of oscillator control register writes has no effect. the values written to unlock the register must be ordered correctly, but are not necessarily consecutive. it is possible to write to or read from other registers within the unlockin g/locking operation. when selecting a new clock source, the primary oscillator failure detection circuitry and the watchdog timer oscillator failure circu itry must be disabled. if pofen and wofen are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a failure of either oscillator. the failure dete ction circuitry can be enabled anytime after a successful write of oscsel in the oscillator control register. the internal precision oscillator is enabled by default. if the user code changes to a different oscillator, it is appropriate to disable the ipo for power savings. disabling the ipo does not occur automatically. clock failure detection and recovery primary oscillator failure z8 encore! xp ? f0823 series devices can generate non-maskable interrupt-like events when the primary oscillator fails. to maintain system function in this situation, the clock failure recovery circuitry auto matically forces the watchdog timer oscillator to drive the system clock. the watchdog timer oscillator must be enabled to allow the recovery. although this oscillator runs at a much slower speed than th e original system clock, the cpu continues to operate, allo wing execution of a clock failure vector and software rou- tines that either remedy the oscillator failure or issue a failure alert. this automatic switch- over is not available if the watchdog timer is the primary oscillator. it is also unavailable if the watchdog timer oscillator is disabled , though it is not necessary to enable the watchdog timer reset fu nction outlined in the watchdog timer on page 87. the primary oscillator failure detection circ uitry asserts if the system clock frequency drops below 1 khz 50%. if an external signal is selected as the system oscillator, it is possible that a very slow but non-failing cloc k can generate a failu re condition. under these conditions, do not enable the clock failure circuitry (p ofen must be deasserted in the oscctl register). caution:
ps024314-0308 oscillator control z8 encore! xp ? f0823 series product specification 167 watchdog timer failure in the event of a watchdog timer oscillator failure, a similar non-maskable interrupt-like event is issued. this event does not trigger an attendant clock switch-over, but alerts the cpu of the failure. after a watchdog timer fa ilure, it is no longer possible to detect a primary oscillator failure. the failure detectio n circuitry does not function if the watchdog timer is used as the primary oscillator or if the watchdog timer oscillator has been dis- abled. for either of these cases, it is necessar y to disable the detection circuitry by deas- serting the wdfen bit of the oscctl register. the watchdog timer oscillator failure detec tion circuit counts system clocks while searching for a watchdog timer clock. the logi c counts 8004 system clock cycles before determining that a failure has occurred. the system clock rate determines the speed at which the watchdog timer failur e can be detected. a very sl ow system clock results in very slow detection times. it is possible to disable the clock failure detection circuitry as well as all functioning clock sources. in this case, the z8 enco re! xp f0823 series device ceases functioning and can only be recovered by power-on reset. oscillator control register definitions the following section provides the bit definitions for the os cillator control register. oscillator control register the oscillator control register (oscctl) enab les/disables the various oscillator circuits, enables/disables the failure detection/recovery circuitry and selects the primary oscillator, which becomes th e system clock. the oscillator control register must be un locked before writing. writing the two step sequence e7h followed by 18h to the oscillator control regi ster unlocks it. the register is locked at successful completion of a register write to the oscctl. table 102. oscillator control register (oscctl) bits 7 6 5 4 3 2 1 0 field inten reserved wdten pofen wdfen scksel reset 10100000 r/w r/wr/wr/wr/wr/wr/wr/wr/w addr f86h caution:
ps024314-0308 oscillator control z8 encore! xp ? f0823 series product specification 168 inten?internal precision oscillator enable 1 = internal precision oscillator is enabled 0 = internal precision oscillator is disabled reserved?r/w bits must be 0 during writes; 0 when read wdten?watchdog timer oscillator enable 1 = watchdog timer oscillator is enabled 0 = watchdog timer oscillator is disabled pofen?primary oscillator failure detection enable 1 = failure detection and recovery of primary oscillator is enabled 0 = failure detection and recovery of primary oscillator is disabled wdfen?watchdog timer oscillato r failure detection enable 1 = failure detection of watch dog timer oscillator is enabled 0 = failure detection of watch dog timer oscillator is disabled scksel?system clock oscillator select 000 = internal precision oscillator functions as system clock at 5.53 mhz 001 = internal precision oscillator functions as system clock at 32 khz 010 = reserved 011 = watchdog timer oscillator functions as system clock 100 = external clock signal on pb3 functions as system clock 101 = reserved 110 = reserved 111 = reserved
ps024314-0308 internal precision oscillator z8 encore! xp ? f0823 series product specification 169 internal precision oscillator the internal precision oscillator (ipo) is de signed for use without external components. you can either manually trim the oscillato r for a non-standard frequency or use the automatic factory-trimmed version to achieve a 5.53 mhz frequency. the features of ipo include: ? on-chip rc oscillator that does not require external components ? output frequency of either 5.53 mhz or 32.8 khz (contains both a fast and a slow mode) ? trimming possible through flash option bits with user override ? elimination of crystals or cer amic resonators in applicati ons where high timing accuracy is not required operation an 8-bit trimming register, incorporated into the design, compensates for absolute varia- tion of oscillator frequency. once trimmed the o scillator frequency is stable and does not require subsequent calibration. trimming is performed during manufacturing and is not necessary for you to repeat unless a frequency other than 5.53 mhz (fast mode) or 32.8 khz (slow mode) is requir ed. this trimming is done at +3 0 c and a supply voltage of 3.3 v, so accuracy of this op erating point is optimal. power down this block for minimum system powe r. by default, the o scillator is configured through the flash option bits. however, the user code can override these trim values as described in trim bit address space on page 146. select one of the two frequencies for the o scillator: 5.53 mhz and 32.8 khz, using the oscsel bits in the oscillator control on page 165.
ps024314-0308 internal precision oscillator z8 encore! xp ? f0823 series product specification 170
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 171 ez8 cpu instruction set assembly language programming introduction the ez8 cpu assembly language provides a me ans for writing an application program without concern for actual memory addresses or machine instruction formats. a program written in assembly language is called a sour ce program. assembly language allows the use of symbolic addresses to identify memory locations. it also allows mnemonic codes (opcodes and operands) to represent the inst ructions themselves. th e opcodes identify the instruction while the operands represent memo ry locations, registers, or immediate data values. each assembly language program consists of a series of symbolic commands called statements. each statement can contain la bels, operations, operands, and comments. labels are assigned to a particular instru ction step in a source program. the label identifies that step in the program as an entry point for use by other instructions. the assembly language also includes assembl er directives that supplement the machine instruction. the assembler directives, or p seudo-ops, are not transl ated into a machine instruction. rather, the pseudo-ops are interp reted as directives that control or assist the assembly process. the source program is processed (assembled) by the assembler to obtain a machine language program called the obje ct code. the object code is executed by the ez8 cpu. an example segment of an assembly language pr ogram is detailed in the following example. assembly language source program example jp start ; everything after the semicolon is a comment. start: ; a label called ?start?. the first instruction ( jp start ) in this ; example causes program execution to jump to the point within the ; program where the start label occurs. ld r4, r7 ; a load (ld) instruction with two operands. the first operand, ; working register r4, is the de stination. the second operand, ; working register r7, is the so urce. the contents of r7 is ; written into r4. ld 234h, #%01 ; another load (ld) instruction with two operands. ; the first operand, extend ed mode register address 234h , ; identifies the destination. the second operand, immediate data ; value 01h , is the source. the value 01h is written into the ; register at address 234h .
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 172 assembly language syntax for proper instruction execution, ez8 cpu ass embly language syntax requires that the operands be written as ?destination, source?. af ter assembly, the obj ect code usually has the operands in the order ?source, destination?, but ordering is opcode-dependent. the following instruction ex amples illustrate the format of some basic assembly instructions and the resulting object code produced by th e assembler. you must follow this binary for- mat if you prefer manual program coding or intend to implement your own assembler. example 1 if the contents of registers 43h and 08h are added and the result is stored in 43h , the assembly syntax and resulting object code is: example 2 in general, when an instructio n format requires an 8-bit register address, that address can specify any register location in the range 0?255 or, using escaped mode addressing, a working register r0?r15. if the contents of register 43h and working register r8 are added and the result is stored in 43h , the assembly syntax and resulting object code is: see the device-specific product specification to determine the exact register file range available. the register file size va ries, depending on the device type. ez8 cpu instruction notation in the ez8 cpu instruction summary and description sections, th e operands, condition codes, status flags, and addr ess modes are represented by a notational shorthand that is described in table 105. table 103. assembly language syntax example 1 assembly language code add 43h, 08h (add dst, src) object code 04 08 43 (opc src, dst) table 104. assembly language syntax example 2 assembly language code add 43h, r8 (add dst, src) object code 04 e8 43 (opc src, dst)
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 173 . table 105. notational shorthand notation description operand range b bit b b represents a value from 0 to 7 (000b to 111b). cc condition code ? see condition codes overview in the ez8 cpu user manual. da direct address addrs addrs represents a number in the range of 0000h to ffffh. er extended addressing register reg reg repres ents a number in the range of 000h to fffh. im immediate data #data data is a number between 00h to ffh. ir indirect working register @rn n = 0?15. ir indirect register @reg reg. represents a number in the range of 00h to ffh. irr indirect working register pair @rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. irr indirect register pair @reg reg represents an even number in the range 00h to feh p polarity p polarity is a single bit binary value of either 0b or 1b. r working register rn n = 0?15. r register reg reg. represents a number in the range of 00h to ffh. ra relative address x x represents an index in the range of +127 to ? 128 which is an offset relative to the address of the next instruction rr working register pair rrp p = 0, 2, 4, 6, 8, 10, 12, or 14. rr register pair reg reg. represents an even number in the range of 00h to feh. vector vector address vector vector represents a number in the range of 00h to ffh. x indexed #index the register or regist er pair to be indexed is offset by the signed index value (#index) in a +127 to -128 range.
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 174 table 106 lists additional symbols th at are used throughout the instruction summary and instruction set description sections. assignment of a value is indicated by an arrow. for example, dst dst + src indicates the source data is ad ded to the destination data and the result is stored in the destination location. ez8 cpu instruction classes ez8 cpu instructions are divided func tionally into the following groups: ? arithmetic ? bit manipulation ? block transfer ? cpu control ? load ? logical ? program control table 106. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix sp stack pointer pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 175 ? rotate and shift tables 107 through table 114 contain the instructions be longing to each group and the number of operands required for each instruction. some instru ctions appear in more than one table as these instruction can be considered as a subset of more than one category. within these tables, the sour ce operand is identified as ?src ?, the destination operand is ?dst? and a condition code is ?cc?. table 107. arithmetic instructions mnemonic operands instruction adc dst, src add with carry adcx dst, src add with carry using extended addressing add dst, src add addx dst, src add using extended addressing cp dst, src compare cpc dst, src compare with carry cpcx dst, src compare with carry using extended addressing cpx dst, src compare using extended addressing da dst decimal adjust dec dst decrement decw dst decrement word inc dst increment incw dst increment word mult dst multiply sbc dst, src subtract with carry sbcx dst, src subtract with carry using extended addressing sub dst, src subtract subx dst, src subtract us ing extended addressing
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 176 table 108. bit manipulation instructions mnemonic operands instruction bclr bit, dst bit clear bit p, bit, dst bit set or clear bset bit, dst bit set bswap dst bit swap ccf ? complement carry flag rcf ? reset carry flag scf ? set carry flag tcm dst, src test complement under mask tcmx dst, src test complement under mask using extended addressing tm dst, src test under mask tmx dst, src test under mask using extended addressing table 109. block transfer instructions mnemonic operands instruction ldci dst, src load constant to/from program memory and auto-increment addresses ldei dst, src load external data to/fr om data memory and auto-increment addresses table 110. cpu control instructions mnemonic operands instruction atm ? atomic execution ccf ? complement carry flag di ? disable interrupts ei ? enable interrupts halt ? halt mode nop ? no operation rcf ? reset carry flag
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 177 scf ? set carry flag srp src set register pointer stop ? stop mode wdt ? watchdog timer refresh table 111. load instructions mnemonic operands instruction clr dst clear ld dst, src load ldc dst, src load constant to/from program memory ldci dst, src load constant to/from program memory and auto-increment addresses lde dst, src load external data to/from data memory ldei dst, src load external data to/f rom data memory and auto-increment addresses ldwx dst, src load word using extended addressing ldx dst, src load using extended addressing lea dst, x(src) load effective address pop dst pop popx dst pop using extended addressing push src push pushx src push using extended addressing table 112. logical instructions mnemonic operands instruction and dst, src logical and andx dst, src logical and using extended addressing com dst complement or dst, src logical or table 110. cpu control instructions (continued) mnemonic operands instruction
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 178 orx dst, src logical or using extended addressing xor dst, src logical exclusive or xorx dst, src logical exclusive or using extended addressing table 113. program control instructions mnemonic operands instruction brk ? on-chip debugger break btj p, bit, src, da bit test and jump btjnz bit, src, da bit test and jump if non-zero btjz bit, src, da bit test and jump if zero call dst call procedure djnz dst, src, ra decrement and jump non-zero iret ? interrupt return jp dst jump jp cc dst jump conditional jr da jump relative jr cc da jump relative conditional ret ? return trap vector software trap table 114. rotate and shift instructions mnemonic operands instruction bswap dst bit swap rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry table 112. logical instructions (continued) mnemonic operands instruction
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 179 ez8 cpu instruction summary table 115 summarizes the ez8 cpu instructions. the table identifies the addressing modes employed by the instruction, the effect upon the flags register, the number of cpu clock cycles required for th e instruction fetch, and the number of cpu clock cycles required for the instruction execution. . sra dst shift right arithmetic srl dst shift right logical swap dst swap nibbles table 115. ez8 cpu instruction summary assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh adc dst, src dst dst + src + c r r 12 ****0* 2 3 rir 13 24 rr 14 3 3 rir 15 3 4 rim 16 3 3 ir im 17 3 4 adcx dst, src dst dst + src + c er er 18 ****0* 4 3 er im 19 4 3 add dst, src dst dst + src r r 02 ****0* 2 3 rir 03 24 rr 04 3 3 rir 05 3 4 rim 06 3 3 ir im 07 3 4 addx dst, src dst dst + src er er 08 ****0* 4 3 er im 09 4 3 flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 table 114. rotate and shift instructions (continued) mnemonic operands instruction
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 180 and dst, src dst dst and src r r 52 ? * * 0 ? ? 2 3 rir 53 24 rr 54 3 3 rir 55 3 4 rim 56 3 3 ir im 57 3 4 andx dst, src dst dst and src er er 58 ? * * 0 ? ? 4 3 er im 59 4 3 atm block all interrupt and dma requests during execution of the next 3 instructions 2f ????? ? 1 2 bclr bit, dst dst[bit] 0 r e2 ????? ? 2 2 bit p, bit, dst dst[bit] p r e2 ???0? ? 2 2 brk debugger break 00 ? ? ? ? ? ? 1 1 bset bit, dst dst[bit] 1 r e2 ???0? ? 2 2 bswap dst dst[7:0] dst[0:7] r d5 x * * 0 ? ? 2 2 btj p, bit, src, dst if src[bit] = p pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjnz bit, src, dst if src[bit] = 1 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 btjz bit, src, dst if src[bit] = 0 pc pc + x r f6 ????? ? 3 3 ir f7 3 4 call dst sp sp -2 @sp pc pc dst irr d4 ????? ? 2 6 da d6 3 3 ccf c ~c ef * ?????- 1 2 clr dst dst 00h r b0 ? ? ? ? ? ? 2 2 ir b1 2 3 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 181 com dst dst ~dst r 60 ? * * 0 ? ? 2 2 ir 61 2 3 cp dst, src dst - src r r a2 ****?? 2 3 rir a3 24 rr a4 3 3 rir a5 3 4 rim a6 3 3 ir im a7 3 4 cpc dst, src dst - src - c r r 1f a2 ****?? 3 3 rir1f a3 34 rr1f a4 4 3 rir1f a5 4 4 rim1f a6 4 3 ir im 1f a7 4 4 cpcx dst, src dst - src - c er er 1f a8 ****?? 5 3 er im 1f a9 5 3 cpx dst, src dst - src er er a8 ****?? 4 3 er im a9 4 3 da dst dst da(dst) r 40 * * * x ? ? 2 2 ir 41 2 3 dec dst dst dst - 1 r 30 ?***?? 2 2 ir 31 2 3 decw dst dst dst - 1 rr 80 ?***?? 2 5 irr 81 2 6 di irqctl[7] 0 8f ????? ? 1 2 djnz dst, ra dst dst ? 1 if dst 0 pc pc + x r 0a-fa ????? ? 2 3 ei irqctl[7] 1 9f ????? ? 1 2 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 182 halt halt mode 7f ? ? ? ? ? ? 1 2 inc dst dst dst + 1 r 20 ? * * ? ? ? 2 2 ir 21 2 3 r0e-fe 12 incw dst dst dst + 1 rr a0 ?***?? 2 5 irr a1 2 6 iret flags @sp sp sp + 1 pc @sp sp sp + 2 irqctl[7] 1 bf ***** * 1 5 jp dst pc dst da 8d ????? ? 3 2 irr c4 2 3 jp cc, dst if cc is true pc dst da 0d-fd ????? ? 3 2 jr dst pc pc + x da 8b ????? ? 2 2 jr cc, dst if cc is true pc pc + x da 0b-fb ????? ? 2 2 ld dst, rc dst src r im 0c-fc ? ? ? ? ? ? 2 2 r x(r) c7 3 3 x(r) r d7 3 4 rir e3 23 rr e4 3 2 rir e5 3 4 rim e6 3 2 ir im e7 3 3 ir r f3 2 3 ir r f5 3 3 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 183 ldc dst, src dst src r irr c2 ????? ? 2 5 ir irr c5 2 9 irr r d2 2 5 ldci dst, src dst src r r + 1 rr rr + 1 ir irr c3 ????? ? 2 9 irr ir d3 2 9 lde dst, src dst src r irr 82 ????? ? 2 5 irr r 92 2 5 ldei dst, src dst src r r + 1 rr rr + 1 ir irr 83 ????? ? 2 9 irr ir 93 2 9 ldwx dst, src dst src er er 1fe8 ????? ? 5 4 ldx dst, src dst src r er 84 ????? ? 3 2 ir er 85 3 3 rirr 86 3 4 ir irr 87 3 5 r x(rr) 88 3 4 x(rr) r 89 3 4 er r 94 3 2 er ir 95 3 3 irr r 96 3 4 irr ir 97 3 5 er er e8 4 2 er im e9 4 2 lea dst, x(src) dst src + x r x(r) 98 ? ? ? ? ? ? 3 3 rr x(rr) 99 3 5 mult dst dst[15:0] dst[15:8] * dst[7:0] rr f4 ????? ? 2 8 nop no operation 0f ? ? ? ? ? ? 1 2 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 184 or dst, src dst dst or src r r 42 ? * * 0 ? ? 2 3 rir 43 24 rr 44 3 3 rir 45 3 4 rim 46 3 3 ir im 47 3 4 orx dst, src dst dst or src er er 48 ? * * 0 ? ? 4 3 er im 49 4 3 pop dst dst @sp sp sp + 1 r 50 ????? ? 2 2 ir 51 2 3 popx dst dst @sp sp sp + 1 er d8 ????? ? 3 2 push src sp sp ? 1 @sp src r 70 ????? ? 2 2 ir 71 2 3 im if70 3 2 pushx src sp sp ? 1 @sp src er c8 ????? ? 3 2 rcf c 0 cf 0???? ? 1 2 ret pc @sp sp sp + 2 af ????? ? 1 4 rl dst r 90 ****?? 2 2 ir 91 2 3 rlc dst r 10 ****?? 2 2 ir 11 2 3 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 185 rr dst r e0 ****?? 2 2 ir e1 2 3 rrc dst r c0 ****?? 2 2 ir c1 2 3 sbc dst, src dst dst ? src - c r r 32 ****1* 2 3 rir 33 24 rr 34 3 3 rir 35 3 4 rim 36 3 3 ir im 37 3 4 sbcx dst, src dst dst ? src - c er er 38 ****1* 4 3 er im 39 4 3 scf c 1 df 1???? ? 1 2 sra dst r d0 * * * 0 ? ? 2 2 ir d1 2 3 srl dst r 1f c0 * * 0 * ? ? 3 2 ir 1f c1 3 3 srp src rp src im 01 ????? ? 2 2 stop stop mode 6f ? ? ? ? ? ? 1 2 sub dst, src dst dst ? src r r 22 ****1* 2 3 rir 23 24 rr 24 3 3 rir 25 3 4 rim 26 3 3 ir im 27 3 4 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1 d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c d7 d6 d5 d4 d3 d2 d1 d0 dst c 0
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 186 subx dst, src dst dst ? src er er 28 ****1* 4 3 er im 29 4 3 swap dst dst[7:4] ? dst[3:0] r f0 x * * x ? ? 2 2 ir f1 2 3 tcm dst, src (not dst) and src r r 62 ? * * 0 ? ? 2 3 rir 63 24 rr 64 3 3 rir 65 3 4 rim 66 3 3 ir im 67 3 4 tcmx dst, src (not dst) and src er er 68 ? * * 0 ? ? 4 3 er im 69 4 3 tm dst, src dst and src r r 72 ? * * 0 ? ? 2 3 rir 73 24 rr 74 3 3 rir 75 3 4 rim 76 3 3 ir im 77 3 4 tmx dst, src dst and src er er 78 ? * * 0 ? ? 4 3 er im 79 4 3 trap vector sp sp ? 2 @sp pc sp sp ? 1 @sp flags pc @vector vector f2 ????? ? 2 6 wdt 5f ????? ? 1 2 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 ez8 cpu instruction set z8 encore! xp ? f0823 series product specification 187 xor dst, src dst dst xor src r r b2 ? * * 0 ? ? 2 3 rir b3 24 rr b4 3 3 rir b5 3 4 rim b6 3 3 ir im b7 3 4 xorx dst, src dst dst xor src er er b8 ? * * 0 ? ? 4 3 er im b9 4 3 table 115. ez8 cpu instruction summary (continued) assembly mnemonic symbolic operation address mode opcode(s) (hex) flags fetch cycles instr. cycles dst src czsvdh flags notation: * = value is a functi on of the result of the operation. ? = unaffected x = undefined 0 = reset to 0 1 = set to 1
ps024314-0308 opcode maps z8 encore! xp ? f0823 series product specification 188 opcode maps a description of the opcode map data an d the abbreviations are provided in figure 26 . figure 27 and figure 28 provide information about each of the ez8 cpu instructions. table 116 lists opcode map abbreviations. figure 26. opcode map cell description cp 3.3 r2,r1 a 4 opcode lower nibble second operand after assembly first operand after assembly opcode upper nibble instruction cycles fetch cycles
ps024314-0308 opcode maps z8 encore! xp ? f0823 series product specification 189 table 116. opcode map abbreviations abbreviation description abbreviation description b bit position irr indirect register pair cc condition code p polarity (0 or 1) x 8-bit signed index or displacement r 4-bit working register da destination address r 8-bit register er extended addressing register r1, r1, ir1, irr1, ir1, rr1, rr1, irr1, er1 destination address im immediate data value r2, r2, ir2, irr2, ir2, rr2, rr2, irr2, er2 source address ir indirect working register ra relative ir indirect register rr working register pair irr indirect working register pair rr register pair
ps024314-0308 opcode maps z8 encore! xp ? f0823 series product specification 190 figure 27. first opcode map cp 3.3 r2,r1 cp 3.4 ir2,r1 cp 2.3 r1,r2 cp 2.4 r1,ir2 cpx 4.3 er2,er1 cpx 4.3 im,er1 cp 3.3 r1,im cp 3.4 ir1,im rrc 2.2 r1 rrc 2.3 ir1 0 1 2 3 4 5 6 7 8 9abcde f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) brk 1.1 srp 2.2 im add 2.3 r1,r2 add 2.4 r1,ir2 add 3.3 r2,r1 add 3.4 ir2,r1 add 3.3 r1,im add 3.4 ir1,im addx 4.3 er2,er1 addx 4.3 im,er1 djnz 2.3 r1,x jr 2.2 cc,x ld 2.2 r1,im jp 3.2 cc,da inc 1.2 r1 nop 1.2 rlc 2.2 r1 rlc 2.3 ir1 adc 2.3 r1,r2 adc 2.4 r1,ir2 adc 3.3 r2,r1 adc 3.4 ir2,r1 adc 3.3 r1,im adc 3.4 ir1,im adcx 4.3 er2,er1 adcx 4.3 im,er1 inc 2.2 r1 inc 2.3 ir1 sub 2.3 r1,r2 sub 2.4 r1,ir2 sub 3.3 r2,r1 sub 3.4 ir2,r1 sub 3.3 r1,im sub 3.4 ir1,im subx 4.3 er2,er1 subx 4.3 im,er1 dec 2.2 r1 dec 2.3 ir1 sbc 2.3 r1,r2 sbc 2.4 r1,ir2 sbc 3.3 r2,r1 sbc 3.4 ir2,r1 sbc 3.3 r1,im sbc 3.4 ir1,im sbcx 4.3 er2,er1 sbcx 4.3 im,er1 da 2.2 r1 da 2.3 ir1 or 2.3 r1,r2 or 2.4 r1,ir2 or 3.3 r2,r1 or 3.4 ir2,r1 or 3.3 r1,im or 3.4 ir1,im orx 4.3 er2,er1 orx 4.3 im,er1 pop 2.2 r1 pop 2.3 ir1 and 2.3 r1,r2 and 2.4 r1,ir2 and 3.3 r2,r1 and 3.4 ir2,r1 and 3.3 r1,im and 3.4 ir1,im andx 4.3 er2,er1 andx 4.3 im,er1 com 2.2 r1 com 2.3 ir1 tcm 2.3 r1,r2 tcm 2.4 r1,ir2 tcm 3.3 r2,r1 tcm 3.4 ir2,r1 tcm 3.3 r1,im tcm 3.4 ir1,im tcmx 4.3 er2,er1 tcmx 4.3 im,er1 push 2.2 r2 push 2.3 ir2 tm 2.3 r1,r2 tm 2.4 r1,ir2 tm 3.3 r2,r1 tm 3.4 ir2,r1 tm 3.3 r1,im tm 3.4 ir1,im tmx 4.3 er2,er1 tmx 4.3 im,er1 decw 2.5 rr1 decw 2.6 irr1 lde 2.5 r1,irr2 ldei 2.9 ir1,irr2 ldx 3.2 r1,er2 ldx 3.3 ir1,er2 ldx 3.4 irr2,r1 ldx 3.5 irr2,ir1 ldx 3.4 r1,rr2,x ldx 3.4 rr1,r2,x rl 2.2 r1 rl 2.3 ir1 lde 2.5 r2,irr1 ldei 2.9 ir2,irr1 ldx 3.2 r2,er1 ldx 3.3 ir2,er1 ldx 3.4 r2,irr1 ldx 3.5 ir2,irr1 lea 3.3 r1,r2,x lea 3.5 rr1,rr2,x incw 2.5 rr1 incw 2.6 irr1 clr 2.2 r1 clr 2.3 ir1 xor 2.3 r1,r2 xor 2.4 r1,ir2 xor 3.3 r2,r1 xor 3.4 ir2,r1 xor 3.3 r1,im xor 3.4 ir1,im xorx 4.3 er2,er1 xorx 4.3 im,er1 ldc 2.5 r1,irr2 ldci 2.9 ir1,irr2 ldc 2.5 r2,irr1 ldci 2.9 ir2,irr1 jp 2.3 irr1 ldc 2.9 ir1,irr2 ld 3.4 r1,r2,x pushx 3.2 er2 sra 2.2 r1 sra 2.3 ir1 popx 3.2 er1 ld 3.4 r2,r1,x call 2.6 irr1 bswap 2.2 r1 call 3.3 da ld 3.2 r2,r1 ld 3.3 ir2,r1 bit 2.2 p,b,r1 ld 2.3 r1,ir2 ldx 4.2 er2,er1 ldx 4.2 im,er1 ld 3.2 r1,im ld 3.3 ir1,im rr 2.2 r1 rr 2.3 ir1 mult 2.8 rr1 ld 3.3 r2,ir1 trap 2.6 vector ld 2.3 ir1,r2 btj 3.3 p,b,r1,x btj 3.4 p,b,ir1,x swap 2.2 r1 swap 2.3 ir1 rcf 1.2 wdt 1.2 stop 1.2 halt 1.2 di 1.2 ei 1.2 ret 1.4 iret 1.5 scf 1.2 ccf 1.2 opcode see 2nd map 1, 2 atm
ps024314-0308 opcode maps z8 encore! xp ? f0823 series product specification 191 figure 28. second opcode map after 1fh cpc 4.3 r2,r1 cpc 4.4 ir2,r1 cpc 3.3 r1,r2 cpc 3.4 r1,ir2 cpcx 5.3 er2,er1 cpcx 5.3 im,er1 cpc 4.3 r1,im cpc 4.4 ir1,im srl 3.2 r1 srl 3.3 ir1 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f lower nibble (hex) upper nibble (hex) 3, 2 push im ldwx 5, 4 er2,er1
ps024314-0308 opcode maps z8 encore! xp ? f0823 series product specification 192
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 193 electrical characteristics the data in this chapter is pre-qualificatio n and pre-characterization and is subject to change. additional electrical characteristics may be found in the individual chapters. absolute maximum ratings stresses greater than those listed in table 117 may cause permanent damage to the device. these ratings are stress ratings only. operation of the device at any condition outside those indicated in the operational s ections of these specifications is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. for improved reliability, tie unused in puts to one of the supply voltages (v dd or v ss ). table 117. absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias -40 +105 c storage temperature -65 +150 c voltage on any pin with respect to v ss -0.3 +5.5 v 1 -0.3 +3.9 v 2 voltage on v dd pin with respect to v ss -0.3 +3.6 v maximum current on input and/or inactive output pin -5 +5 a maximum output current from active output pin -25 +25 ma 8-pin packages maximum ratings at 0 c to 70 c total power dissipation 220 mw maximum current into v dd or out of v ss 60 ma 20-pin packages maximum ratings at 0 c to 70 c total power dissipation 430 mw maximum current into v dd or out of v ss 120 ma 28-pin packages maximum ratings at 0 c to 70 c total power dissipation 450 mw
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 194 dc characteristics table 118 lists the dc characteristics of the z8 encore! xp ? f0823 series products. all voltages are referenced to v ss , the primary system ground. maximum current into v dd or out of v ss 125 ma operating temperature is spec ified in dc characteristics. 1. this voltage applies to all pins except the following: v dd , av dd , pins supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). on the 8-pin packages, this applies to all pins but v dd . 2. this voltage applies to pins on the 20/28 pin packages supporting analog input (port b[5:0], port c[2:0]) and pins supporting the crystal oscillator (pa0 and pa1). table 118. dc characteristics symbol parameter t a = -40 c to +105 c (unless otherwise specified) units conditions minimum typical maximum v dd supply voltage 2.7 ? 3.6 v v il1 low level input voltage -0.3 ? 0.3*v dd v v ih1 high level input voltage 0.7*v dd ? 5.5 v for all input pins without analog or oscillator function. for all signal pins on the 8-pin devices. programmable pull-ups must also be disabled. v ih2 high level input voltage 0.7*v dd ?v dd +0.3 v for those pins with analog or oscillator function (20-/28-pin devices only), or when programmable pull-ups are enabled. v ol1 low level output voltage ??0.4vi ol = 2 ma; v dd = 3.0 v high output drive disabled. v oh1 high level output voltage 2.4 ? ? v i oh = -2 ma; v dd = 3.0 v high output drive disabled. v ol2 low level output voltage ??0.6vi ol = 20 ma; v dd = 3.3 v high output drive enabled. table 117. absolute maximum ratings (continued) parameter minimum maximum units notes
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 195 v oh2 high level output voltage 2.4 ? ? v i oh = -20 ma; v dd = 3.3 v high output drive enabled. i ih input leakage current ?+ 0.002 + 5av in = v dd v dd = 3.3 v; i il input leakage current ?+ 0.007 + 5av in = v ss v dd = 3.3 v; i tl tristate leakage current ??+ 5a i led controlled current drive 1.8 3 4.5 ma {afs2,afs1} = {0,0} 2.8 7 10.5 ma {afs2,afs1} = {0,1} 7.8 13 19.5 ma {afs2,afs1} = {1,0} 12 20 30 ma {afs2,afs1} = {1,1} c pad gpio port pad capacitance ?8.0 2 ?pf c xin xin pad capacitance ?8.0 2 ?pf c xout xout pad capacitance ?9.5 2 ?pf i pu weak pull-up current 30 100 350 a v dd = 3.0 v?3.6 v v ram ram data retention voltage tbd v voltage at which ram retains static values; no reading or writing is allowed. notes 1. this condition excludes all pins that have on-chip pull-ups, when driven low. 2. these values are provided for design guid ance only and are not tested in production. table 118. dc characteristics (continued) symbol parameter t a = -40 c to +105 c (unless otherwise specified) units conditions minimum typical maximum
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 196 table 119. power consumption symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum 2 std temp maximum 3 ext temp i dd stop supply current in stop mode 0.1 2 7.5 a no peripherals enabled. all pins driven to v dd or v ss . i dd halt supply current in halt mode (with all peripherals disabled) 35 55 65 a 32 khz 520 630 700 a 5.5 mhz i dd supply current in active mode (with all peripherals disabled) 2.8 4.5 4.8 ma 32 khz 4.5 5.2 5.2 ma 5.5 mhz i dd wdt watchdog timer supply current 0.9 1.0 1.1 a i dd ipo internal precision oscillator supply current 350 500 550 a i dd vbo voltage brownout supply current 50 a for 20-/28-pin devices (vbo only); see note 4 for 8-pin devices; see note 4 i dd adc analog-to-digital converter supply current (with external reference) 2.8 3.1 3.2 ma 32 khz 3.1 3.6 3.7 ma 5.5 mhz 3.3 3.7 3.8 ma 10 mhz 3.7 4.2 4.3 ma 20 mhz i dd adcref adc internal reference supply current 0asee note 4 i dd cmp comparator supply current 150 180 190 a see note 4
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 197 ac characteristics the section provides information about the ac characteristics and timing. all ac timing information assumes a standard load of 50 pf on all outputs. i dd bg band gap supply current 320 480 500 a for 20-/28-pin devices for 8-pin devices notes 1. typical conditions are defined as v dd = 3.3 v and +30 c. 2. standard temperature is defined as t a = 0 c to +70 c; these values not tested in production for worst case behavior, but are derived from product characterization and provided for design guidance only. 3. extended temperature is defined as t a = -40 c to +105 c; these values not tested in production for worst case behavior, but are derived from product characterization and provided for design guidance only. 4. for this block to operate, the band gap circuit is automatically turned on and must be added to the total supply current. this bandgap current is only added once, re gardless of how many peripherals are using it. table 120. ac characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum maximum f sysclk system clock frequency ? 20.0 1 mhz read-only from flash memory 0.032768 20.0 1 mhz program or erasure of the flash memory t xin system clock period 50 ? ns t clk = 1/f sysclk t xinh system clock high time 20 30 ns t clk = 50 ns t xinl system clock low time 20 30 ns t clk = 50 ns t xinr system clock rise time ? 3 ns t clk = 50 ns t xinf system clock fall time ? 3 ns t clk = 50 ns 1 system clock frequency is limited by the intern al precision oscillator on the z8 encore! xp ? f0823 series. see table 121 on page 198. table 119. power consumption (continued) symbol parameter v dd = 2.7 v to 3.6 v units conditions typical 1 maximum 2 std temp maximum 3 ext temp
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 198 table 121. internal precision oscillator electrical characteristics symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum typical maximum f ipo internal precision oscillator frequency (high speed) 5.53 mhz v dd = 3.3 v t a = 30 c f ipo internal precision oscillator frequency (low speed) 32.7 khz v dd = 3.3 v t a = 30 c f ipo internal precision oscillator error + 1+ 4% t ipost internal precision oscillator startup time 3s
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 199 on-chip peripheral ac and dc electrical characteristics table 122. power-on reset and voltage brownout electrical characteristics and timing symbol parameter t a = -40 c to +105 c units conditions minimum typical 1 maximum v por power-on reset voltage threshold 2.20 2.45 2.70 v v dd = v por v vbo voltage brownout reset voltage threshold 2.15 2.40 2.65 v v dd = v vbo v por to v vbo hysteresis 50 75 mv starting v dd voltage to ensure valid power-on reset. ?v ss ?v t ana power-on reset analog delay ?70 ?sv dd > v por ; t por digital reset delay follows t ana t por power-on reset digital delay 16 s 66 internal precision oscillator cycles + ipo startup time (t ipost ) t smr stop mode recovery 16 s 66 internal precision oscillator cycles t vbo voltage brownout pulse rejection period ? 10 ? s period of time in which v dd < v vbo without generating a reset. t ramp time for v dd to transition from v ss to v por to ensure valid reset 0.10 ? 100 ms t smp stop mode recovery pin pulse rejection period 20 ns for any smr pin or for the reset pin when it is asserted in stop mode. 1 data in the typical column is from characterization at 3.3 v and 30 c. these values are provided for design guidance only and are not tested in production.
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 200 table 123. flash memory electrical characteristics and timing parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units notes minimum typical maximum flash byte read time 100 ? ? ns flash byte program time 20 ? 40 s flash page erase time 10 ? ? ms flash mass erase time 200 ? ? ms writes to single address before next erase ?? 2 flash row program time ? ? 8 ms cumulative program time for single row cannot exceed limit before next erase. this parameter is only an issue when bypassing the flash controller. data retention 100 ? ? years 25 c endurance 10,000 ? ? cycles program/erase cycles table 124. watchdog timer electrical characteristics and timing symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c (unless otherwise stated) units conditions minimum typical maximum f wdt wdt oscillator frequency 10 khz f wdt wdt oscillator error + 50 % t wdtcal wdt calibrated timeout 0.98 1 1.02 s v dd = 3.3 v; t a = 30 c 0.70 1 1.30 s v dd = 2.7 v to 3.6 v t a = 0 c to 70 c 0.50 1 1.50 s v dd = 2.7 v to 3.6 v t a = -40 c to +105 c
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 201 table 125. analog-to-digital converter electrical characteristics and timing symbol parameter v dd = 3.0 v to 3.6 v t a = 0 c to +70 c (unless otherwise stated) units conditions minimum typical maximum resolution 10 ? bits differential nonlinearity (dnl) -1.0 ? 1.0 lsb 3 external v ref = 2.0 v; r s 3.0 k ? integral nonlinearity (inl) -3.0 ? 3.0 lsb 3 external v ref = 2.0 v; r s 3.0 k ? offset error with calibration + 1lsb 3 absolute accuracy with calibration + 3lsb 3 v ref internal reference voltage 1.0 2.0 1.1 2.2 1.2 2.4 v refsel=01 refsel=10 v ref internal reference variation with temperature + 1.0 % temperature variation with v dd = 3.0 v ref internal reference voltage variation with v dd + 0.5 % supply voltage variation with t a = 30 c r refout reference buffer output impedance 850 ? when the internal reference is buffered and driven out to the vref pin (refout = 1) single-shot conversion time ? 5129 ? system clock cycles all measurements but temperature sensor 10258 temperature sensor measurement continuous conversion time ? 256 ? system clock cycles all measurements but temperature sensor 512 temperature sensor measurement signal input bandwidth ? 10 khz as defined by -3 db point r s analog source impedance 4 ??10k ? in unbuffered mode
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 202 table 126. comparator electrical characteristics general purpose i/o port input data sample timing figure 29 displays timing of the gpio port i nput sampling. the input value on a gpio port pin is sampled on the rising edge of the system clock. the port value is available to the ez8 cpu on the second rising clock edge following the change of the port value. zin input impedance ? 150 k ? in unbuffered mode at 20 mhz 5 vin input voltage range 0 v dd v unbuffered mode notes 1. analog source impedance affects the adc offset volt age (because of pin leakage) and input settling time. 2. devices are factory calibrated at v dd = 3.3 v and t a = +30 c, so the adc is maximally accurate under these conditions. 3. lsbs are defined assuming 10-bit resolution. 4. this is the maximum recommended resistance seen by the adc input pin. 5. the input impedance is inversely proportional to the system clock frequency. symbol parameter v dd = 2.7 v to 3.6 v t a = -40 c to +105 c units conditions minimum typical maximum v os input dc offset 5 mv v cref programmable internal reference voltage + 5 % 20-/28-pin devices + 3 % 8-pin devices t prop propagation delay 200 ns v hys input hysteresis 4 mv v in input voltage range v ss v dd -1 v table 125. analog-to-digital converter electrical characteristics and timing (continued) symbol parameter v dd = 3.0 v to 3.6 v t a = 0 c to +70 c (unless otherwise stated) units conditions minimum typical maximum
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 203 figure 29. port input sample timing table 127. gpio port input timing parameter abbreviation delay (ns) minimum maximum t s_port port input transition to xin ris e setup time (not pictured) 5 ? t h_port xin rise to port input transition hold time (not pictured) 0 ? t smr gpio port pin pulse width to ensure stop mode recovery (for gpio port pins enabled as smr sources) 1 s system tclk port pin port value changes to 0 0 latched into port input input value port input data register latch clock data register port input data read on data bus port input data register value 0 read by ez8
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 204 general purpose i/o port output timing figure 30 and table 128 provide timing information for gpio port pins. figure 30. gpio port output timing table 128. gpio port output timing parameter abbreviation delay (ns) minimum maximum gpio port pins t 1 xin rise to port output valid delay ? 15 t 2 xin rise to port ou tput hold time 2 ? xin port output tclk t1 t2
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 205 on-chip debugger timing figure 31 and table 129 provide timing information for the dbg pin. the dbg pin timing specifications assume a 4 ns maximum rise and fall time. figure 31. on-chip debugger timing table 129. on-chip debugger timing parameter abbreviation delay (ns) minimum maximum dbg t 1 xin rise to dbg valid delay ? 15 t 2 xin rise to dbg output hold time 2 ? t 3 dbg to xin rise input setup time 5 ? t 4 dbg to xin rise input hold time 5 ? xin dbg tclk t1 t2 (output) dbg t3 t4 (input) output data input data
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 206 uart timing figure 32 and table 130 provide timing information for uart pins for the case where cts is used for flow control. the cts to de assertion delay (t1) assumes the transmit data register has been loaded with data prior to cts assertion. figure 32. uart timing with cts table 130. uart timing with cts parameter abbreviation delay (ns) minimum maximum uart t 1 cts fall to de output delay 2 * xin period 2 * xin period + 1 bit time t 2 de assertion to txd falling e dge (start bit) delay 5 t 3 end of stop bit(s) to de deassertion delay 5 cts de t1 (output) txd t2 (output) (input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) t3
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 207 figure 33 and table 131 provide timing information for uart pins for the case where cts is not used for flow cont rol. de asserts after the transmit data register has been written. de remains asserted for multiple characters as long as th e transmit data register is written with the next character before the current character has completed. figure 33. uart timing without cts table 131. uart timing without cts parameter abbreviation delay (ns) minimum maximum uart t 1 de assertion to txd falling edge (start bit) delay 1 * xin period 1 bit time t 2 end of stop bit(s) to de deassertion delay (tx data register is empty) 5 de t1 (output) txd t2 (output) start bit0 bit 1 bit 7 parity stop end of stop bit(s)
ps024314-0308 electrical characteristics z8 encore! xp ? f0823 series product specification 208
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 209 packaging figure 34 displays the 8-pin plastic dual in line package (pdip) available for the z8 encore! xp ? f0823 series devices. figure 34. 8-pin plastic dual inline package (pdip) ea e b1 q1 b s a2 l e a1 c d e1 1 8 4 5 controlling dimensions : mm.
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 210 figure 35 displays the 8-pin small outline integr ated circuit package (soic) available for the z8 encore! xp f0823 series devices. figure 35. 8-pin small outline in tegrated circuit package (soic)
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 211 figure 36 displays the 8-pin quad flat no-lea d package (qfn)/mlf-s available for the z8 encore! xp f0823 series devices. this pack age has a footprint iden tical to that of the 8-pin soic, but with a lower profile. figure 36. 8-pin quad flat no-lead package (qfn)/mlf-s figure 37 displays the 20-pin plastic dual inline package (pdip) available for z8 encore! xp f0823 series devices. figure 37. 20-pin plastic dual inline package (pdip)
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 212 figure 38 displays the 20-pin smal l outline integrated circuit package (soic) available for z8 encore! xp f0823 series devices. figure 38. 20-pin small outline integrated circuit package (soic) figure 39 displays the 20-pin small shrink outline package (sso p) available for z8 encore! xp f0823 series devices. figure 39. 20-pin small shri nk outline package (ssop)
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 213 figure 40 displays the 28-pin plastic dual inline package (pdip) available for z8 encore! xp f0823 series devices. figure 40. 28-pin plastic dual inline package (pdip)
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 214 figure 41 displays the 28-pin smal l outline integrated circuit package (soic) available in z8 encore! xp f0823 series devices. figure 41. 28-pin small outline integrated circuit package (soic)
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 215 figure 42 displays the 28-pin small shrink outline package (sso p) available for z8 encore! xp f0823 series devices. figure 42. 28-pin small shri nk outline package (ssop) symbol a a1 b c a2 e millimeter inch min max min max 1.73 0.05 1.68 0.25 5.20 0.65 typ 0.09 10.07 7.65 0.63 1.86 0.0256 typ 0.13 10.20 1.73 7.80 5.30 1.99 0.21 1.78 0.75 0.068 0.002 0.066 0.010 0.205 0.004 0.397 0.301 0.025 0.073 0.005 0.068 0.209 0.006 0.402 0.307 0.030 0.078 0.008 0.070 0.015 0.212 0.008 0.407 0.311 0.037 0.38 0.20 10.33 5.38 7.90 0.95 nom nom d e h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 114 seating plane a2 e a q1 a1 b l 0 - 8
ps024314-0308 packaging z8 encore! xp ? f0823 series product specification 216
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 217 ordering information part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description z8 encore! xp with 8 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0823pb005sc 8 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0823qb005sc 8 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0823sb005sc 8 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0823sh005sc 8 kb 1 kb 16 18 2 7 1 soic 20-pin package z8f0823hh005sc 8 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0823ph005sc 8 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0823sj005sc 8 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0823hj005sc 8 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0823pj005sc 8 kb 1 kb 22 18 2 8 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0823pb005ec 8 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0823qb005ec 8 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0823sb005ec 8 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0823sh005ec 8 kb 1 kb 16 18 2 7 1 soic 20-pin package z8f0823hh005ec 8 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0823ph005ec 8 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0823sj005ec 8 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0823hj005ec 8 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0823pj005ec 8 kb 1 kb 22 18 2 8 1 pdip 28-pin package replace c with g for lead-free packaging
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 218 z8 encore! xp with 8 kb flash standard temperature: 0 c to 70 c z8f0813pb005sc 8 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0813qb005sc 8 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0813sb005sc 8 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0813sh005sc 8 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0813hh005sc 8 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0813ph005sc 8 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0813sj005sc 8 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0813hj005sc 8 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0813pj005sc 8 kb 1 kb 24 18 2 0 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0813pb005ec 8 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0813qb005ec 8 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0813sb005ec 8 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0813sh005ec 8 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0813hh005ec 8 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0813ph005ec 8 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0813sj005ec 8 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0813hj005ec 8 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0813pj005ec 8 kb 1 kb 24 18 2 0 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 219 z8 encore! xp with 4 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0423pb005sc 4 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0423qb005sc 4 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0423sb005sc 4 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0423sh005sc 4 kb 1 kb 16 18 2 7 1 soic 20-pin package z8f0423hh005sc 4 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0423ph005sc 4 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0423sj005sc 4 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0423hj005sc 4 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0423pj005sc 4 kb 1 kb 22 18 2 8 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0423pb005ec 4 kb 1 kb 6 12 2 4 1 pdip 8-pin package z8f0423qb005ec 4 kb 1 kb 6 12 2 4 1 qfn 8-pin package z8f0423sb005ec 4 kb 1 kb 6 12 2 4 1 soic 8-pin package z8f0423sh005ec 4 kb 1 kb 16 18 2 7 1 soic 20-pin package Z8F0423HH005EC 4 kb 1 kb 16 18 2 7 1 ssop 20-pin package z8f0423ph005ec 4 kb 1 kb 16 18 2 7 1 pdip 20-pin package z8f0423sj005ec 4 kb 1 kb 22 18 2 8 1 soic 28-pin package z8f0423hj005ec 4 kb 1 kb 22 18 2 8 1 ssop 28-pin package z8f0423pj005ec 4 kb 1 kb 22 18 2 8 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 220 z8 encore! xp with 4 kb flash standard temperature: 0 c to 70 c z8f0413pb005sc 4 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0413qb005sc 4 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0413sb005sc 4 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0413sh005sc 4 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0413hh005sc 4 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0413ph005sc 4 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0413sj005sc 4 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0413hj005sc 4 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0413pj005sc 4 kb 1 kb 24 18 2 0 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0413pb005ec 4 kb 1 kb 6 12 2 0 1 pdip 8-pin package z8f0413qb005ec 4 kb 1 kb 6 12 2 0 1 qfn 8-pin package z8f0413sb005ec 4 kb 1 kb 6 12 2 0 1 soic 8-pin package z8f0413sh005ec 4 kb 1 kb 16 18 2 0 1 soic 20-pin package z8f0413hh005ec 4 kb 1 kb 16 18 2 0 1 ssop 20-pin package z8f0413ph005ec 4 kb 1 kb 16 18 2 0 1 pdip 20-pin package z8f0413sj005ec 4 kb 1 kb 24 18 2 0 1 soic 28-pin package z8f0413hj005ec 4 kb 1 kb 24 18 2 0 1 ssop 28-pin package z8f0413pj005ec 4 kb 1 kb 24 18 2 0 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 221 z8 encore! xp with 2 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0223pb005sc 2 kb 512 b 6 12 2 4 1 pdip 8-pin package z8f0223qb005sc 2 kb 512 b 6 12 2 4 1 qfn 8-pin package z8f0223sb005sc 2 kb 512 b 6 12 2 4 1 soic 8-pin package z8f0223sh005sc 2 kb 512 b 16 18 2 7 1 soic 20-pin package z8f0223hh005sc 2 kb 512 b 16 18 2 7 1 ssop 20-pin package z8f0223ph005sc 2 kb 512 b 16 18 2 7 1 pdip 20-pin package z8f0223sj005sc 2 kb 512 b 22 18 2 8 1 soic 28-pin package z8f0223hj005sc 2 kb 512 b 22 18 2 8 1 ssop 28-pin package z8f0223pj005sc 2 kb 512 b 22 18 2 8 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0223pb005ec 2 kb 512 b 6 12 2 4 1 pdip 8-pin package z8f0223qb005ec 2 kb 512 b 6 12 2 4 1 qfn 8-pin package z8f0223sb005ec 2 kb 512 b 6 12 2 4 1 soic 8-pin package z8f0223sh005ec 2 kb 512 b 16 18 2 7 1 soic 20-pin package z8f0223hh005ec 2 kb 512 b 16 18 2 7 1 ssop 20-pin package z8f0223ph005ec 2 kb 512 b 16 18 2 7 1 pdip 20-pin package z8f0223sj005ec 2 kb 512 b 22 18 2 8 1 soic 28-pin package z8f0223hj005ec 2 kb 512 b 22 18 2 8 1 ssop 28-pin package z8f0223pj005ec 2 kb 512 b 22 18 2 8 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 222 z8 encore! xp with 2 kb flash standard temperature: 0 c to 70 c z8f0213pb005sc 2 kb 512 b 6 12 2 0 1 pdip 8-pin package z8f0213qb005sc 2 kb 512 b 6 12 2 0 1 qfn 8-pin package z8f0213sb005sc 2 kb 512 b 6 12 2 0 1 soic 8-pin package z8f0213sh005sc 2 kb 512 b 16 18 2 0 1 soic 20-pin package z8f0213hh005sc 2 kb 512 b 16 18 2 0 1 ssop 20-pin package z8f0213ph005sc 2 kb 512 b 16 18 2 0 1 pdip 20-pin package z8f0213sj005sc 2 kb 512 b 24 18 2 0 1 soic 28-pin package z8f0213hj005sc 2 kb 512 b 24 18 2 0 1 ssop 28-pin package z8f0213pj005sc 2 kb 512 b 24 18 2 0 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0213pb005ec 2 kb 512 b 6 12 2 0 1 pdip 8-pin package z8f0213qb005ec 2 kb 512 b 6 12 2 0 1 qfn 8-pin package z8f0213sb005ec 2 kb 512 b 6 12 2 0 1 soic 8-pin package z8f0213sh005ec 2 kb 512 b 16 18 2 0 1 soic 20-pin package z8f0213hh005ec 2 kb 512 b 16 18 2 0 1 ssop 20-pin package z8f0213ph005ec 2 kb 512 b 16 18 2 0 1 pdip 20-pin package z8f0213sj005ec 2 kb 512 b 24 18 2 0 1 soic 28-pin package z8f0213hj005ec 2 kb 512 b 24 18 2 0 1 ssop 28-pin package z8f0213pj005ec 2 kb 512 b 24 18 2 0 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 223 z8 encore! xp with 1 kb flash, 10-bit analog-to-digital converter standard temperature: 0 c to 70 c z8f0123pb005sc 1 kb 256 b 6 12 2 4 1 pdip 8-pin package z8f0123qb005sc 1 kb 256 b 6 12 2 4 1 qfn 8-pin package z8f0123sb005sc 1 kb 256 b 6 12 2 4 1 soic 8-pin package z8f0123sh005sc 1 kb 256 b 16 18 2 7 1 soic 20-pin package z8f0123hh005sc 1 kb 256 b 16 18 2 7 1 ssop 20-pin package z8f0123ph005sc 1 kb 256 b 16 18 2 7 1 pdip 20-pin package z8f0123sj005sc 1 kb 256 b 22 18 2 8 1 soic 28-pin package z8f0123hj005sc 1 kb 256 b 22 18 2 8 1 ssop 28-pin package z8f0123pj005sc 1 kb 256 b 22 18 2 8 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0123pb005ec 1 kb 256 b 6 12 2 4 1 pdip 8-pin package z8f0123qb005ec 1 kb 256 b 6 12 2 4 1 qfn 8-pin package z8f0123sb005ec 1 kb 256 b 6 12 2 4 1 soic 8-pin package z8f0123sh005ec 1 kb 256 b 16 18 2 7 1 soic 20-pin package z8f0123hh005ec 1 kb 256 b 16 18 2 7 1 ssop 20-pin package z8f0123ph005ec 1 kb 256 b 16 18 2 7 1 pdip 20-pin package z8f0123sj005ec 1 kb 256 b 22 18 2 8 1 soic 28-pin package z8f0123hj005ec 1 kb 256 b 22 18 2 8 1 ssop 28-pin package z8f0123pj005ec 1 kb 256 b 22 18 2 8 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 224 z8 encore! xp with 1 kb flash standard temperature: 0 c to 70 c z8f0113pb005sc 1 kb 256 b 6 12 2 0 1 pdip 8-pin package z8f0113qb005sc 1 kb 256 b 6 12 2 0 1 qfn 8-pin package z8f0113sb005sc 1 kb 256 b 6 12 2 0 1 soic 8-pin package z8f0113sh005sc 1 kb 256 b 16 18 2 0 1 soic 20-pin package z8f0113hh005sc 1 kb 256 b 16 18 2 0 1 ssop 20-pin package z8f0113ph005sc 1 kb 256 b 16 18 2 0 1 pdip 20-pin package z8f0113sj005sc 1 kb 256 b 24 18 2 0 1 soic 28-pin package z8f0113hj005sc 1 kb 256 b 24 18 2 0 1 ssop 28-pin package z8f0113pj005sc 1 kb 256 b 24 18 2 0 1 pdip 28-pin package extended temperature: -40 c to 105 c z8f0113pb005ec 1 kb 256 b 6 12 2 0 1 pdip 8-pin package z8f0113qb005ec 1 kb 256 b 6 12 2 0 1 qfn 8-pin package z8f0113sb005ec 1 kb 256 b 6 12 2 0 1 soic 8-pin package z8f0113sh005ec 1 kb 256 b 16 18 2 0 1 soic 20-pin package z8f0113hh005ec 1 kb 256 b 16 18 2 0 1 ssop 20-pin package z8f0113ph005ec 1 kb 256 b 16 18 2 0 1 pdip 20-pin package z8f0113sj005ec 1 kb 256 b 24 18 2 0 1 soic 28-pin package z8f0113hj005ec 1 kb 256 b 24 18 2 0 1 ssop 28-pin package z8f0113pj005ec 1 kb 256 b 24 18 2 0 1 pdip 28-pin package replace c with g for lead-free packaging part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 225 z8 encore! xp ? f0823 series development kit z8f08a28100kitg z8 encore! xp f082a se ries development kit (20- and 28-pin) z8f04a28100kitg z8 encore! xp f042a se ries development kit (20- and 28-pin) z8f04a08100kitg z8 encore! xp f042a series development kit (8-pin) zusbsc00100zacg usb smart cable accessory kit zusboptsc01zacg opto-isolated usb smart cable accessory kit zenetsc0100zacg ethernet smart cable accessory kit part number flash ram i/o lines interrupts 16-bit timers w/pwm 10-bit a/d channels uart with irda description
ps024314-0308 ordering information z8 encore! xp ? f0823 series product specification 226 part number suffix designations z8 f 04 23 s h 005 s c environmental flow c = standard plastic packaging compound g = green plastic packaging compound temperature range s = standard, 0 c to 70 c e = extended, -40 c to +105 c speed 020 = 20 mhz pin count b = 8 h = 20 j = 28 package h = ssop p = pdip s = soic device type 23 = 6-22 i/o lines, 4-8 adc channels 13 = 6-24 i/o lines, no adc channels memory size 08 = 8 kb flash, 1 kb ram 04 = 4 kb flash, 1 kb ram 02 = 2 kb flash, 512 b ram 01 = 1 kb flash, 256 b ram memory type f = flash device family z8 = zilog?s 8-bit microcontroller
z8 encore! xp ? f0823 series product specification ps024314-0308 index 227 index symbols # 174 % 174 @ 174 numerics 10-bit adc 4 40-lead plastic dual-inline package 214, 215 a absolute maximum ratings 193 ac characteristics 197 adc 175 architecture 117 automatic power-down 118 block diagram 118 continuous conversion 120 control register 122, 124 control register definitions 122 data high byte register 124 data low bits register 125 electrical characteristics and timing 201 operation 118 single-shot conversion 119 adcctl register 122, 124 adcdh register 124 adcdl register 125 adcx 175 add 175 add - extended addressing 175 add with carry 175 add with carry - extended addressing 175 additional symbols 174 address space 13 addx 175 analog signals 10 analog-to-digital converter (adc) 117 and 177 andx 177 arithmetic instructions 175 assembly language programming 171 assembly language syntax 172 b b 174 b 173 baud rate generator, uart 103 bclr 176 binary number suffix 174 bit 176 bit 173 clear 176 manipulation instructions 176 set 176 set or clear 176 swap 176 test and jump 178 test and jump if non-zero 178 test and jump if zero 178 bit jump and test if non-zero 178 bit swap 178 block diagram 3 block transfer instructions 176 brk 178 bset 176 bswap 176, 178 btj 178 btjnz 178 btjz 178 c call procedure 178 capture mode 84, 85 capture/compare mode 85 cc 173 ccf 176 characteristics, electrical 193 clear 177 clr 177 com 177
z8 encore! xp ? f0823 series product specification ps024314-0308 index 228 compare 84 compare - extended addressing 175 compare mode 84 compare with carry 175 compare with carry - extended addressing 175 complement 177 complement carry flag 176 condition code 173 continuous conversion (adc) 120 continuous mode 84 control register definition, uart 104 control registers 13, 17 counter modes 84 cp 175 cpc 175 cpcx 175 cpu and peripheral overview 4 cpu control instructions 176 cpx 175 customer support 237 d da 173, 175 data memory 15 dc characteristics 194 debugger, on-chip 151 dec 175 decimal adjust 175 decrement 175 decrement and jump non-zero 178 decrement word 175 decw 175 destination operand 174 device, port availability 35 di 176 direct address 173 disable interrupts 176 djnz 178 dst 174 e ei 176 electrical characteristics 193 adc 201 flash memory and timing 200 gpio input data sample timing 202 watchdog timer 200, 202 enable interrupt 176 er 173 extended addressing register 173 external pin reset 25 ez8 cpu features 4 ez8 cpu instruction classes 174 ez8 cpu instruction notation 172 ez8 cpu instruction set 171 ez8 cpu instruction summary 179 f fctl register 137, 143, 144 features, z8 encore! 1 first opcode map 190 flags 174 flags register 174 flash controller 4 option bit address space 144 option bit configuration - reset 141 program memory address 0000h 144 program memory address 0001h 145 flash memory 129 arrangement 130 byte programming 135 code protection 133 configurations 129 control register definitions 137, 143 controller bypass 136 electrical characteristics and timing 200 flash control register 137, 143, 144 flash option bits 134 flash status register 137 flow chart 132 frequency high and low byte registers 139 mass erase 135 operation 131 operation timing 133
z8 encore! xp ? f0823 series product specification ps024314-0308 index 229 page erase 135 page select register 138, 139 fps register 138, 139 fstat register 137 g gated mode 84 general-purpose i/o 35 gpio 4, 35 alternate functions 36 architecture 36 control register definitions 43 input data sample timing 202 interrupts 43 port a-c pull-up enable sub-registers 48, 49 port a-h address registers 44 port a-h alternate function sub-registers 45 port a-h control registers 44 port a-h data direction sub-registers 45 port a-h high drive enable sub-registers 47 port a-h input data registers 49 port a-h output control sub-registers 46 port a-h output data registers 50 port a-h stop mode recovery sub-registers 47 port availability by device 35 port input timing 203 port output timing 204 h h 174 halt 176 halt mode 32, 176 hexadecimal number prefix/suffix 174 i i2c 4 im 173 immediate data 173 immediate operand prefix 174 inc 175 increment 175 increment word 175 incw 175 indexed 173 indirect address prefix 174 indirect register 173 indirect register pair 173 indirect working register 173 indirect working register pair 173 infrared encoder/decoder (irda) 113 instruction set 171 instruction set, ez8 cpu 171 instructions adc 175 adcx 175 add 175 addx 175 and 177 andx 177 arithmetic 175 bclr 176 bit 176 bit manipulation 176 block transfer 176 brk 178 bset 176 bswap 176, 178 btj 178 btjnz 178 btjz 178 call 178 ccf 176 clr 177 com 177 cp 175 cpc 175 cpcx 175 cpu control 176 cpx 175 da 175 dec 175 decw 175 di 176
z8 encore! xp ? f0823 series product specification ps024314-0308 index 230 djnz 178 ei 176 halt 176 inc 175 incw 175 iret 178 jp 178 ld 177 ldc 177 ldci 176, 177 lde 177 ldei 176 ldx 177 lea 177 load 177 logical 177 mult 175 nop 176 or 177 orx 178 pop 177 popx 177 program control 178 push 177 pushx 177 rcf 176 ret 178 rl 178 rlc 178 rotate and shift 178 rr 178 rrc 178 sbc 175 scf 176, 177 sra 179 srl 179 srp 177 stop 177 sub 175 subx 175 swap 179 tcm 176 tcmx 176 tm 176 tmx 176 trap 178 watchdog timer refresh 177 xor 178 xorx 178 instructions, ez8 classes of 174 interrupt control register 64 interrupt controller 53 architecture 53 interrupt assertion types 56 interrupt vectors and priority 56 operation 55 register definitions 58 software interrupt assertion 57 interrupt edge select register 63 interrupt request 0 register 58 interrupt request 1 register 59 interrupt request 2 register 59 interrupt return 178 interrupt vector listing 53 interrupts uart 101 ir 173 ir 173 irda architecture 113 block diagram 113 control register definitions 116 operation 113 receiving data 115 transmitting data 114 iret 178 irq0 enable high and low bit registers 60 irq1 enable high and low bit registers 61 irq2 enable high and low bit registers 62 irr 173 irr 173 j jp 178 jump, conditional, relative, and relative condi- tional 178
z8 encore! xp ? f0823 series product specification ps024314-0308 index 231 l ld 177 ldc 177 ldci 176, 177 lde 177 ldei 176, 177 ldx 177 lea 177 load 177 load constant 176 load constant to/from program memory 177 load constant with auto-increment addresses 177 load effective address 177 load external data 177 load external data to/from data memory and auto-increment addresses 176 load external to/from data memory and auto-in- crement addresses 177 load instructions 177 load using extended addressing 177 logical and 177 logical and/extended addressing 177 logical exclusive or 178 logical exclusive or/extended addressing 178 logical instructions 177 logical or 177 logical or/extended addressing 178 low power modes 31 m master interrupt enable 55 memory data 15 program 13 mode capture 84, 85 capture/compare 85 continuous 84 counter 84 gated 84 one-shot 84 pwm 84, 85 modes 84 mult 175 multiply 175 multiprocessor mode, uart 99 n nop (no operation) 176 notation b 173 cc 173 da 173 er 173 im 173 ir 173 ir 173 irr 173 irr 173 p 173 r 173 r 173 ra 173 rr 173 rr 173 vector 173 x 173 notational shorthand 173 o ocd architecture 151 auto-baud detector/generator 154 baud rate limits 155 block diagram 151 breakpoints 156 commands 157 control register 161 data format 154 dbg pin to rs-232 interface 152 debug mode 153 debugger break 178 interface 152 serial errors 155
z8 encore! xp ? f0823 series product specification ps024314-0308 index 232 status register 163 timing 205 ocd commands execute instruction (12h) 161 read data memory (0dh) 160 read ocd control register (05h) 158 read ocd revision (00h) 158 read ocd status register (02h) 158 read program counter (07h) 159 read program memory (0bh) 160 read program memory crc (0eh) 161 read register (09h) 159 read runtime counter (03h) 158 step instruction (10h) 161 stuff instruction (11h) 161 write data memory (0ch) 160 write ocd control register (04h) 158 write program counter (06h) 159 write program memory (0ah) 159 write register (08h) 159 on-chip debugger (ocd) 151 on-chip debugger signals 10 one-shot mode 84 opcode map abbreviations 189 cell description 188 first 190 second after 1fh 191 operational description 21, 31, 35, 53, 67, 87, 93, 113, 117, 127, 129, 141, 151, 165, 169 or 177 ordering information 217 orx 178 p p 173 packaging 20-pin pdip 211, 212 20-pin ssop 212, 215 28-pin pdip 213 28-pin soic 214 8-pin pdip 209 8-pin soic 210 pdip 214, 215 part selection guide 2 pc 174 pdip 214, 215 peripheral ac and dc electrical characteristics 199 pin characteristics 10 pin descriptions 7 polarity 173 pop 177 pop using extended addressing 177 popx 177 port availability, device 35 port input timing (gpio) 203 port output timing, gpio 204 power supply signals 10 power-down, automatic (adc) 118 power-on and voltage brownout electrical characteristics and timing 199 power-on reset (por) 23 program control instructions 178 program counter 174 program memory 13 push 177 push using extended addressing 177 pushx 177 pwm mode 84, 85 pxaddr register 44 pxctl register 45 r r 173 r 173 ra register address 173 rcf 176 receive irda data 115 receiving uart data-interrupt-driven method 98 receiving uart data-polled method 97 register 173 adc control (adcctl) 122, 124
z8 encore! xp ? f0823 series product specification ps024314-0308 index 233 adc data high byte (adcdh) 124 adc data low bits (adcdl) 125 flash control (fctl) 137, 143, 144 flash high and low byte (ffreqh and freeql) 139 flash page select (fps) 138, 139 flash status (fstat) 137 gpio port a-h address (pxaddr) 44 gpio port a-h alternate function sub-regis- ters 46 gpio port a-h control address (pxctl) 45 gpio port a-h data direction sub-registers 45 ocd control 161 ocd status 163 uartx baud rate high byte (uxbrh) 110 uartx baud rate low byte (uxbrl) 110 uartx control 0 (uxctl0) 107, 110 uartx control 1 (uxctl1) 108 uartx receive data (uxrxd) 105 uartx status 0 (uxstat0) 105 uartx status 1 (uxstat1) 106 uartx transmit data (uxtxd) 104 watchdog timer control (wdtctl) 90, 128 watch-dog timer control (wdtctl) 167 watchdog timer reload high byte (wdth) 91 watchdog timer reload low byte (wdtl) 91 watchdog timer reload upper byte (wd- tu) 91 register file 13 register pair 173 register pointer 174 reset and stop mode characteristics 22 and stop mode recovery 21 carry flag 176 sources 22 ret 178 return 178 rl 178 rlc 178 rotate and shift instructions 178 rotate left 178 rotate left through carry 178 rotate right 178 rotate right through carry 178 rp 174 rr 173, 178 rr 173 rrc 178 s sbc 175 scf 176, 177 second opcode map after 1fh 191 set carry flag 176, 177 set register pointer 177 shift right arithmetic 179 shift right logical 179 signal descriptions 9 single-sho conversion (adc) 119 software trap 178 source operand 174 sp 174 sra 179 src 174 srl 179 srp 177 stack pointer 174 stop 177 stop mode 31, 177 stop mode recovery sources 26 using a gpio port pin transition 27, 28 using watchdog timer time-out 27 sub 175 subtract 175 subtract - extended addressing 175 subtract with carry 175 subtract with carry - extended addressing 175 subx 175 swap 179 swap nibbles 179 symbols, additional 174
z8 encore! xp ? f0823 series product specification ps024314-0308 index 234 t tcm 176 tcmx 176 test complement under mask 176 test complement under mask - extended ad- dressing 176 test under mask 176 test under mask - extended addressing 176 timer signals 9 timers 67 architecture 67 block diagram 67 capture mode 74, 75, 84, 85 capture/compare mode 78, 85 compare mode 76, 84 continuous mode 69, 84 counter mode 70, 71 counter modes 84 gated mode 77, 84 one-shot mode 68, 84 operating mode 68 pwm mode 72, 73, 84, 85 reading the timer count values 79 reload high and low byte registers 80 timer control register definitions 80 timer output signal operation 79 timers 0-3 control registers 82, 83 high and low byte registers 80, 81 tm 176 tmx 176 tools, hardware and software 226 transmit irda data 114 transmitting uart data-polled method 95 transmitting uart dat-interrupt-driven method 96 trap 178 u uart 4 architecture 93 baud rate generator 103 control register definitions 104 controller signals 9 data format 94 interrupts 101 multiprocessor mode 99 receiving data using interrupt-driven meth- od 98 receiving data using the polled method 97 transmitting data using the interrupt-driven method 96 transmitting data using the polled method 95 x baud rate high and low registers 110 x control 0 and control 1 registers 107 x status 0 and status 1 registers 105, 106 uxbrh register 110 uxbrl register 110 uxctl0 register 107, 110 uxctl1 register 108 uxrxd register 105 uxstat0 register 105 uxstat1 register 106 uxtxd register 104 v vector 173 voltage brownout reset (vbr) 24 w watchdog timer approximate time-out delay 87 cntl 24 control register 89, 127, 167 electrical characteristics and timing 200, 202 interrupt in normal operation 88 interrupt in stop mode 88 refresh 88, 177 reload unlock sequence 89 reload upper, high and low registers 90 reset 25 reset in normal operation 89
z8 encore! xp ? f0823 series product specification ps024314-0308 index 235 reset in stop mode 89 time-out response 88 watchdog timer control register (wdtctl) 90 wdtctl register 90, 128, 167 wdth register 91 wdtl register 91 wdtu register 91 working register 173 working register pair 173 x x 173 xor 178 xorx 178 z z8 encore! block diagram 3 features 1 part selection guide 2
z8 encore! xp ? f0823 series product specification ps024314-0308 index 236
ps024314-0308 customer support z8 encore! xp ? f0823 series product specification 237 customer support for answers to technical questions about the product, documentation, or any other issues with zilog?s offering s, please visit zilog?s knowledge base at http://www.zilog.com/kb . for any comments, detail technical questions, or reporting problems, please visit zilog?s technical support at http://support.zilog.com .

▲Up To Search▲

Price & Availability of Z8F0423HH005EC

	To Download Z8F0423HH005EC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .